command: remove returns to IDLE state (will be better to add a timeout for a transfer and reset the fsm).
This commit is contained in:
parent
8b1522bbc9
commit
7efaef485f
|
@ -125,8 +125,6 @@ class SATACommandRX(Module):
|
||||||
If(test_type("DMA_ACTIVATE_D2H"),
|
If(test_type("DMA_ACTIVATE_D2H"),
|
||||||
dma_activate.eq(1),
|
dma_activate.eq(1),
|
||||||
NextState("WAIT_WRITE_REG_D2H")
|
NextState("WAIT_WRITE_REG_D2H")
|
||||||
).Else(
|
|
||||||
NextState("IDLE") # Generate an error
|
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
@ -135,8 +133,6 @@ class SATACommandRX(Module):
|
||||||
If(transport.source.stb,
|
If(transport.source.stb,
|
||||||
If(test_type("REG_D2H"),
|
If(test_type("REG_D2H"),
|
||||||
NextState("PRESENT_WRITE_RESPONSE")
|
NextState("PRESENT_WRITE_RESPONSE")
|
||||||
).Else(
|
|
||||||
NextState("IDLE") # Generate an error
|
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
@ -154,8 +150,6 @@ class SATACommandRX(Module):
|
||||||
transport.source.ack.eq(0),
|
transport.source.ack.eq(0),
|
||||||
If(test_type("DATA"),
|
If(test_type("DATA"),
|
||||||
NextState("PRESENT_READ_DATA")
|
NextState("PRESENT_READ_DATA")
|
||||||
).Else(
|
|
||||||
NextState("IDLE") # Generate an error
|
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
@ -174,8 +168,6 @@ class SATACommandRX(Module):
|
||||||
If(transport.source.stb,
|
If(transport.source.stb,
|
||||||
If(test_type("REG_D2H"),
|
If(test_type("REG_D2H"),
|
||||||
NextState("PRESENT_READ_RESPONSE")
|
NextState("PRESENT_READ_RESPONSE")
|
||||||
).Else(
|
|
||||||
NextState("IDLE") # Generate an error
|
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|
Loading…
Reference in New Issue