add storage qualifier

This commit is contained in:
Florent Kermarrec 2015-01-27 20:14:07 +01:00
parent fc96b20225
commit 7f9174f83d
5 changed files with 20 additions and 3 deletions

2
README
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@ -44,6 +44,8 @@ external Rx/Tx pins to be ready to debug or control all your Wishbone peripheral
- Logic analyser with LiteScopeLA: - Logic analyser with LiteScopeLA:
- Various triggering modules: Term, Range, Edge (add yours! :) - Various triggering modules: Term, Range, Edge (add yours! :)
- Run Length Encoder to "compress" data and increase recording depth - Run Length Encoder to "compress" data and increase recording depth
- Subsampling
- Storage qualifier
- Data storage in block rams - Data storage in block rams
[> Possibles improvements [> Possibles improvements

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@ -85,6 +85,7 @@ class LiteScopeRecorderUnit(Module):
self.data_sink = data_sink = Sink(data_layout(dw)) self.data_sink = data_sink = Sink(data_layout(dw))
self.trigger = Signal() self.trigger = Signal()
self.qualifier = Signal()
self.length = Signal(bits_for(depth)) self.length = Signal(bits_for(depth))
self.offset = Signal(bits_for(depth)) self.offset = Signal(bits_for(depth))
self.done = Signal() self.done = Signal()
@ -119,7 +120,11 @@ class LiteScopeRecorderUnit(Module):
If(trigger_sink.stb & trigger_sink.hit, NextState("POST_HIT_RECORDING")) If(trigger_sink.stb & trigger_sink.hit, NextState("POST_HIT_RECORDING"))
) )
fsm.act("POST_HIT_RECORDING", fsm.act("POST_HIT_RECORDING",
fifo.sink.stb.eq(data_sink.stb), If(self.qualifier,
fifo.sink.stb.eq(trigger_sink.stb & trigger_sink.hit & data_sink.stb)
).Else(
fifo.sink.stb.eq(data_sink.stb)
),
fifo.sink.data.eq(data_sink.data), fifo.sink.data.eq(data_sink.data),
data_sink.ack.eq(fifo.sink.ack), data_sink.ack.eq(fifo.sink.ack),
@ -131,6 +136,7 @@ class LiteScopeRecorder(LiteScopeRecorderUnit, AutoCSR):
LiteScopeRecorderUnit.__init__(self, dw, depth) LiteScopeRecorderUnit.__init__(self, dw, depth)
self._trigger = CSR() self._trigger = CSR()
self._qualifier = CSRStorage()
self._length = CSRStorage(bits_for(depth)) self._length = CSRStorage(bits_for(depth))
self._offset = CSRStorage(bits_for(depth)) self._offset = CSRStorage(bits_for(depth))
self._done = CSRStatus() self._done = CSRStatus()
@ -143,6 +149,7 @@ class LiteScopeRecorder(LiteScopeRecorderUnit, AutoCSR):
self.comb += [ self.comb += [
self.trigger.eq(self._trigger.re), self.trigger.eq(self._trigger.re),
self.qualifier.eq(self._qualifier.storage),
self.length.eq(self._length.storage), self.length.eq(self._length.storage),
self.offset.eq(self._offset.storage), self.offset.eq(self._offset.storage),
self._done.status.eq(self.done), self._done.status.eq(self.done),

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@ -63,7 +63,11 @@ class LiteScopeLA(Module, AutoCSR):
Record.connect(rle.source, self.recorder.data_sink) Record.connect(rle.source, self.recorder.data_sink)
] ]
else: else:
self.comb += Record.connect(sink, self.recorder.data_sink) self.submodules.delay_buffer = Buffer(self.sink.description)
self.comb += [
Record.connect(sink, self.delay_buffer.d),
Record.connect(self.delay_buffer.q, self.recorder.data_sink)
]
def export(self, vns, filename): def export(self, vns, filename):
def format_line(*args): def format_line(*args):

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@ -187,6 +187,9 @@ class LiteScopeLADriver():
def configure_subsampler(self, n): def configure_subsampler(self, n):
self.subsampler_value.write(n-1) self.subsampler_value.write(n-1)
def configure_qualifier(self, v):
self.recorder_qualifier.write(v)
def configure_rle(self, v): def configure_rle(self, v):
self.rle_enable.write(v) self.rle_enable.write(v)

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@ -8,7 +8,8 @@ la = LiteScopeLADriver(wb.regs, "la", debug=True)
cond = {"cnt0" : 128} # trigger on cnt0 = 128 cond = {"cnt0" : 128} # trigger on cnt0 = 128
la.configure_term(port=0, cond=cond) la.configure_term(port=0, cond=cond)
la.configure_sum("term") la.configure_sum("term")
la.configure_subsampler(16) la.configure_subsampler(1)
la.configure_qualifier(1)
la.run(offset=128, length=256) la.run(offset=128, length=256)
while not la.done(): while not la.done():