Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

fhdl/verilog: fix dummy signal initial event

Browse source
This commit is contained in:
Sebastien Bourdeauducq 2015-03-19 00:24:30 +01:00
parent 3aee58f484
commit 7fa1cd72a8
1 changed files with 2 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
migen/fhdl/verilog.py
View file

@ -184,7 +184,8 @@ def _printcomb(f, ns, display_run):
syn_on = "// synthesis translate_on\n"
dummy_s = Signal(name_override="dummy_s")
r += syn_off
r += "reg " + _printsig(ns, dummy_s) + " = 1'd0;\n"
r += "reg " + _printsig(ns, dummy_s) + ";\n"
r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n"
r += syn_on
groups = group_by_targets(f.comb)