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soc/interconnect/stream_packet: reset_less optimizations

This commit is contained in:
Florent Kermarrec 2017-06-30 19:40:54 +02:00
parent 227b14c3f3
commit 7fcdd94cd4
1 changed files with 5 additions and 3 deletions
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8
litex/soc/interconnect/stream_packet.py
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@ -163,7 +163,7 @@ class Packetizer(Module):
dw = len(self.sink.data) dw = len(self.sink.data)
header_reg = Signal(header.length*8) header_reg = Signal(header.length*8, reset_less=True)
header_words = (header.length*8)//dw header_words = (header.length*8)//dw
load = Signal() load = Signal()
shift = Signal() shift = Signal()
@ -253,6 +253,7 @@ class Depacketizer(Module):
dw = len(sink.data) dw = len(sink.data)
header_reg = Signal(header.length*8, reset_less=True)
header_words = (header.length*8)//dw header_words = (header.length*8)//dw
shift = Signal() shift = Signal()
@ -269,13 +270,14 @@ class Depacketizer(Module):
if header_words == 1: if header_words == 1:
self.sync += \ self.sync += \
If(shift, If(shift,
self.header.eq(sink.data) header_reg.eq(sink.data)
) )
else: else:
self.sync += \ self.sync += \
If(shift, If(shift,
self.header.eq(Cat(self.header[dw:], sink.data)) header_reg.eq(Cat(header_reg[dw:], sink.data))
) )
self.comb += self.header.eq(header_reg)
fsm = FSM(reset_state="IDLE") fsm = FSM(reset_state="IDLE")
self.submodules += fsm self.submodules += fsm