migen.fhdl.std -> migen

misoc/com/gpio.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 

misoc/com/liteethmini/common.py

@@ -1,7 +1,7 @@
 import math
 from collections import OrderedDict
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.record import *
 from migen.genlib.fsm import FSM, NextState

misoc/com/spi/__init__.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 from migen.genlib.fsm import FSM, NextState
 

misoc/com/spi/test/spi_master_tb.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 from migen.sim.generic import run_simulation
 

misoc/com/uart/__init__.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 from migen.bank.eventmanager import *
 from migen.genlib.record import Record

misoc/com/uart/bridge.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 
 from misoc.tools.wishbone import WishboneStreamingBridge
 from misoc.com.uart.phy.serial import UARTPHYSerial

misoc/com/uart/phy/serial.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 from migen.flow.actor import Sink, Source

misoc/com/uart/phy/sim.py

@@ -2,7 +2,7 @@ import os
 import pty
 import time
 
-from migen.fhdl.std import *
+from migen import *
 from migen.flow.actor import Sink, Source
 
 

misoc/cpu/identifier.py

@@ -1,6 +1,6 @@
 import subprocess
 
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 
 def get_id():

misoc/cpu/lm32.py

@@ -1,6 +1,6 @@
 import os
 
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 
 

misoc/cpu/mor1kx.py

@@ -1,6 +1,6 @@
 import os
 
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 
 

misoc/cpu/timer.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 from migen.bank.eventmanager import *
 

misoc/mem/flash/norflash16.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.fsm import FSM, NextState
 

misoc/mem/flash/spiflash.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus.transactions import *
 from migen.bus import wishbone
 from migen.genlib.misc import timeline

misoc/mem/sdram/core/__init__.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 from migen.bank.description import *
 

misoc/mem/sdram/core/lasmibus.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus.transactions import *
 from migen.genlib import roundrobin
 from migen.genlib.record import *

misoc/mem/sdram/core/lasmicon/__init__.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 
 from misoc.mem.sdram.phy import dfi
 from misoc.mem.sdram.core import lasmibus

misoc/mem/sdram/core/lasmicon/bankmachine.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.roundrobin import *
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.misc import optree

misoc/mem/sdram/core/lasmicon/multiplexer.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.roundrobin import *
 from migen.genlib.misc import optree
 from migen.genlib.fsm import FSM, NextState

misoc/mem/sdram/core/lasmicon/perf.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 
 

misoc/mem/sdram/core/lasmicon/refresher.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.misc import timeline
 from migen.genlib.fsm import FSM
 

misoc/mem/sdram/core/lasmixbar.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib import roundrobin
 from migen.genlib.record import *
 from migen.genlib.misc import optree

misoc/mem/sdram/core/minicon/__init__.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.misc import optree, WaitTimer

misoc/mem/sdram/frontend/dma_lasmi.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.flow.actor import *
 from migen.genlib.fifo import SyncFIFO
 

misoc/mem/sdram/frontend/memtest.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.misc import optree
 from migen.bank.description import *
 from migen.actorlib.spi import *

misoc/mem/sdram/frontend/wishbone2lasmi.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fsm import FSM, NextState
 
 class WB2LASMI(Module):

misoc/mem/sdram/module.py

@@ -16,7 +16,7 @@
 
 from math import ceil
 
-from migen.fhdl.std import *
+from migen import *
 from misoc.mem import sdram
 
 

misoc/mem/sdram/phy/dfi.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 
 

misoc/mem/sdram/phy/dfii.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 
 from misoc.mem.sdram.phy import dfi

misoc/mem/sdram/phy/gensdrphy.py

@@ -21,7 +21,7 @@
 # This PHY only supports CAS Latency 2.
 #
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 from migen.fhdl.specials import *
 

misoc/mem/sdram/phy/initsequence.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import log2_int
+from migen import log2_int
 
 
 def get_sdram_phy_header(sdram_phy_settings):

misoc/mem/sdram/phy/k7ddrphy.py

@@ -1,6 +1,6 @@
 # tCK=5ns CL=7 CWL=6
 
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 
 from misoc.mem.sdram.phy.dfi import *

misoc/mem/sdram/phy/s6ddrphy.py

@@ -16,7 +16,7 @@
 # Write commands must be sent on phase 1.
 #
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 
 from misoc.mem.sdram.phy.dfi import *

misoc/mem/sdram/phy/simphy.py

@@ -6,7 +6,7 @@
 # TODO:
 # - add $display support to Migen and manage timing violations?
 
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl.specials import *
 from misoc.mem.sdram.phy.dfi import *
 from misoc.mem import sdram

misoc/mem/sdram/test/abstract_transactions_lasmi.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 

misoc/mem/sdram/test/bankmachine_tb.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
 from misoc.mem.sdram.code import lasmibus

misoc/mem/sdram/test/common.py

@@ -1,7 +1,7 @@
 from fractions import Fraction
 from math import ceil
 
-from migen.fhdl.std import *
+from migen import *
 
 from misoc import sdram
 

misoc/mem/sdram/test/lasmicon_df_tb.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
 from misoc.mem.sdram.core import lasmibus

misoc/mem/sdram/test/lasmicon_tb.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
 from misoc.mem.sdram.core import lasmibus

misoc/mem/sdram/test/lasmicon_wb.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation

misoc/mem/sdram/test/minicon_tb.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus.transactions import TRead, TWrite
 from migen.bus import wishbone
 from migen.sim.generic import Simulator

misoc/mem/sdram/test/refresher.py

@@ -1,6 +1,6 @@
 from random import Random
 
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
 from misoc.mem.sdram.core.lasmicon.refresher import *

misoc/soc/__init__.py

@@ -1,6 +1,6 @@
 from operator import itemgetter
 
-from migen.fhdl.std import *
+from migen import *
 from migen.bank import csrgen
 from migen.bus import wishbone, csr, wishbone2csr
 

misoc/soc/cpuif.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import CSRStatus
 
 

misoc/soc/sdram.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.record import *
 

misoc/tools/wishbone.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.misc import chooser, Counter, WaitTimer
 from migen.genlib.record import Record

misoc/video/dvisampler/__init__.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import AutoCSR
 
 from misoc.video.dvisampler.edid import EDID

misoc/video/dvisampler/analysis.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.record import Record

misoc/video/dvisampler/chansync.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fifo import _inc
 from migen.genlib.record import Record, layout_len

misoc/video/dvisampler/charsync.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.genlib.misc import optree
 from migen.bank.description import *

misoc/video/dvisampler/clocking.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 

misoc/video/dvisampler/datacapture.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
 from migen.bank.description import *
 

misoc/video/dvisampler/debug.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.record import layout_len
 from migen.bank.description import AutoCSR

misoc/video/dvisampler/decoding.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import Record
 
 from misoc.video.dvisampler.common import control_tokens, channel_layout

misoc/video/dvisampler/dma.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fsm import FSM, NextState
 from migen.bank.description import *
 from migen.bank.eventmanager import *

misoc/video/dvisampler/edid.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl.specials import Tristate
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fsm import FSM, NextState

misoc/video/dvisampler/wer.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 from migen.genlib.misc import optree
 from migen.genlib.cdc import PulseSynchronizer

misoc/video/framebuffer/__init__.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.flow.network import *
 from migen.flow import plumbing
 from migen.bank.description import AutoCSR

misoc/video/framebuffer/dvi.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.misc import optree
 
 control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]

misoc/video/framebuffer/format.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.flow.actor import *
 from migen.bank.description import CSRStorage
 from migen.genlib.record import Record

misoc/video/framebuffer/phy.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *

targets/de0nano.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 
 from misoc.mem.sdram.module import IS42S16160
 from misoc.mem.sdram.phy import gensdrphy

targets/kc705.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoc.mem.sdram.module import MT8JTF12864

targets/minispartan6.py

@@ -1,6 +1,6 @@
 from fractions import Fraction
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.actorlib.fifo import SyncFIFO
 

targets/mlabs_video.py

@@ -2,7 +2,7 @@ import os
 from fractions import Fraction
 from math import ceil
 
-from migen.fhdl.std import *
+from migen import *
 from mibuild.generic_platform import ConstraintError
 
 from misoc.mem.sdram.module import MT46V32M16

targets/pipistrello.py

@@ -1,6 +1,6 @@
 from fractions import Fraction
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoc.mem.sdram.module import MT46H32M16

targets/ppro.py

@@ -1,6 +1,6 @@
 from fractions import Fraction
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoc.mem.sdram.module import MT48LC4M16

targets/simple.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.io import CRG
 

targets/versa.py

@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.io import CRG