misoclib -> misoc

make.py

@@ -11,8 +11,8 @@ from mibuild.tools import write_to_file
 from migen.util.misc import autotype
 from migen.fhdl import simplify
 
-from misoclib.soc import cpuif
-from misoclib.mem.sdram.phy import initsequence
+from misoc.soc import cpuif
+from misoc.mem.sdram.phy import initsequence
 
 from misoc_import import misoc_import
 

misoc/com/liteethmini/mac/__init__.py

@@ -1,6 +1,6 @@
-from misoclib.com.liteethmini.common import *
-from misoclib.com.liteethmini.mac.core import LiteEthMACCore
-from misoclib.com.liteethmini.mac.frontend.wishbone import LiteEthMACWishboneInterface
+from misoc.com.liteethmini.common import *
+from misoc.com.liteethmini.mac.core import LiteEthMACCore
+from misoc.com.liteethmini.mac.frontend.wishbone import LiteEthMACWishboneInterface
 
 
 class LiteEthMAC(Module, AutoCSR):

misoc/com/liteethmini/mac/core/__init__.py

@@ -1,7 +1,7 @@
-from misoclib.com.liteethmini.common import *
-from misoclib.com.liteethmini.mac.core import gap, preamble, crc, padding, last_be
-from misoclib.com.liteethmini.phy.sim import LiteEthPHYSim
-from misoclib.com.liteethmini.phy.mii import LiteEthPHYMII
+from misoc.com.liteethmini.common import *
+from misoc.com.liteethmini.mac.core import gap, preamble, crc, padding, last_be
+from misoc.com.liteethmini.phy.sim import LiteEthPHYSim
+from misoc.com.liteethmini.phy.mii import LiteEthPHYMII
 
 
 class LiteEthMACCore(Module, AutoCSR):

misoc/com/liteethmini/mac/core/crc.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteethmini.common import *
+from misoc.com.liteethmini.common import *
 
 
 class LiteEthMACCRCEngine(Module):

misoc/com/liteethmini/mac/core/gap.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteethmini.common import *
+from misoc.com.liteethmini.common import *
 
 class LiteEthMACGap(Module):
     def __init__(self, dw, ack_on_gap=False):

misoc/com/liteethmini/mac/core/last_be.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteethmini.common import *
+from misoc.com.liteethmini.common import *
 
 
 class LiteEthMACTXLastBE(Module):

misoc/com/liteethmini/mac/core/padding.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteethmini.common import *
+from misoc.com.liteethmini.common import *
 
 
 class LiteEthMACPaddingInserter(Module):

misoc/com/liteethmini/mac/core/preamble.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteethmini.common import *
+from misoc.com.liteethmini.common import *
 
 
 class LiteEthMACPreambleInserter(Module):

misoc/com/liteethmini/mac/frontend/sram.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteethmini.common import *
+from misoc.com.liteethmini.common import *
 
 from migen.bank.description import *
 from migen.bank.eventmanager import *

misoc/com/liteethmini/mac/frontend/wishbone.py

@@ -1,5 +1,5 @@
-from misoclib.com.liteethmini.common import *
-from misoclib.com.liteethmini.mac.frontend import sram
+from misoc.com.liteethmini.common import *
+from misoc.com.liteethmini.mac.frontend import sram
 
 from migen.bus import wishbone
 from migen.fhdl.simplify import FullMemoryWE

misoc/com/liteethmini/phy/__init__.py

@@ -1,27 +1,27 @@
-from misoclib.com.liteethmini.common import *
+from misoc.com.liteethmini.common import *
 
 
 def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
     # Autodetect PHY
     if hasattr(pads, "source_stb"):
         # This is a simulation PHY
-        from misoclib.com.liteethmini.phy.sim import LiteEthPHYSim
+        from misoc.com.liteethmini.phy.sim import LiteEthPHYSim
         return LiteEthPHYSim(pads)
     elif hasattr(clock_pads, "gtx") and flen(pads.tx_data) == 8:
         if hasattr(clock_pads, "tx"):
             # This is a 10/100/1G PHY
-            from misoclib.com.liteethmini.phy.gmii_mii import LiteEthPHYGMIIMII
+            from misoc.com.liteethmini.phy.gmii_mii import LiteEthPHYGMIIMII
             return LiteEthPHYGMIIMII(clock_pads, pads, clk_freq=clk_freq, **kwargs)
         else:
             # This is a pure 1G PHY
-            from misoclib.com.liteethmini.phy.gmii import LiteEthPHYGMII
+            from misoc.com.liteethmini.phy.gmii import LiteEthPHYGMII
             return LiteEthPHYGMII(clock_pads, pads, **kwargs)
     elif hasattr(pads, "rx_ctl"):
         # This is a 10/100/1G RGMII PHY
         raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation")
     elif flen(pads.tx_data) == 4:
         # This is a MII PHY
-        from misoclib.com.liteethmini.phy.mii import LiteEthPHYMII
+        from misoc.com.liteethmini.phy.mii import LiteEthPHYMII
         return LiteEthPHYMII(clock_pads, pads, **kwargs)
     else:
         raise ValueError("Unable to autodetect PHY from platform file, use direct instantiation")

misoc/com/liteethmini/phy/gmii.py

@@ -1,6 +1,6 @@
 from migen.genlib.io import DDROutput
 
-from misoclib.com.liteethmini.common import *
+from misoc.com.liteethmini.common import *
 
 
 class LiteEthPHYGMIITX(Module):

misoc/com/liteethmini/phy/gmii_mii.py

@@ -2,11 +2,11 @@ from migen.genlib.io import DDROutput
 from migen.flow.plumbing import Multiplexer, Demultiplexer
 from migen.genlib.cdc import PulseSynchronizer
 
-from misoclib.com.liteethmini.common import *
+from misoc.com.liteethmini.common import *
 
-from misoclib.com.liteethmini.phy.gmii import LiteEthPHYGMIICRG
-from misoclib.com.liteethmini.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
-from misoclib.com.liteethmini.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
+from misoc.com.liteethmini.phy.gmii import LiteEthPHYGMIICRG
+from misoc.com.liteethmini.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
+from misoc.com.liteethmini.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
 
 modes = {
     "GMII": 0,

misoc/com/liteethmini/phy/loopback.py

@@ -1,5 +1,5 @@
-from misoclib.com.liteethmini.common import *
-from misoclib.com.liteethmini.generic import *
+from misoc.com.liteethmini.common import *
+from misoc.com.liteethmini.generic import *
 
 
 class LiteEthPHYLoopbackCRG(Module, AutoCSR):

misoc/com/liteethmini/phy/mii.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteethmini.common import *
+from misoc.com.liteethmini.common import *
 
 
 def converter_description(dw):

misoc/com/liteethmini/phy/s6rgmii.py

@@ -4,7 +4,7 @@ from migen.genlib.io import DDROutput
 from migen.genlib.misc import WaitTimer
 from migen.genlib.fsm import FSM, NextState
 
-from misoclib.com.liteethmini.common import *
+from misoc.com.liteethmini.common import *
 
 
 class LiteEthPHYRGMIITX(Module):

misoc/com/liteethmini/phy/sim.py

@@ -1,6 +1,6 @@
 import os
 
-from misoclib.com.liteethmini.common import *
+from misoc.com.liteethmini.common import *
 
 
 class LiteEthPHYSimCRG(Module, AutoCSR):

misoc/com/spi/test/spi_master_tb.py

@@ -2,7 +2,7 @@ from migen.fhdl.std import *
 from migen.genlib.record import *
 from migen.sim.generic import run_simulation
 
-from misoclib.com.spi import SPIMaster
+from misoc.com.spi import SPIMaster
 
 
 class SPISlave(Module):

misoc/com/uart/bridge.py

@@ -1,7 +1,7 @@
 from migen.fhdl.std import *
 
-from misoclib.tools.wishbone import WishboneStreamingBridge
-from misoclib.com.uart.phy.serial import UARTPHYSerial
+from misoc.tools.wishbone import WishboneStreamingBridge
+from misoc.com.uart.phy.serial import UARTPHYSerial
 
 class UARTWishboneBridge(WishboneStreamingBridge):
     def __init__(self, pads, clk_freq, baudrate=115200):

misoc/com/uart/phy/__init__.py

@@ -1,8 +1,8 @@
 def UARTPHY(pads, *args, **kwargs):
     # Autodetect PHY
     if hasattr(pads, "source_stb"):
-        from misoclib.com.uart.phy.sim import UARTPHYSim
+        from misoc.com.uart.phy.sim import UARTPHYSim
         return UARTPHYSim(pads, *args, **kwargs)
     else:
-        from misoclib.com.uart.phy.serial import UARTPHYSerial
+        from misoc.com.uart.phy.serial import UARTPHYSerial
         return UARTPHYSerial(pads, *args, **kwargs)

misoc/com/uart/software/wishbone.py

@@ -1,6 +1,6 @@
 import serial
 from struct import *
-from misoclib.com.uart.software.reg import *
+from misoc.com.uart.software.reg import *
 
 
 def write_b(uart, data):

misoc/mem/sdram/core/__init__.py

@@ -2,9 +2,9 @@ from migen.fhdl.std import *
 from migen.genlib.record import *
 from migen.bank.description import *
 
-from misoclib.mem.sdram.phy import dfii
-from misoclib.mem.sdram.core import minicon, lasmicon
-from misoclib.mem.sdram.core import lasmixbar
+from misoc.mem.sdram.phy import dfii
+from misoc.mem.sdram.core import minicon, lasmicon
+from misoc.mem.sdram.core import lasmixbar
 
 
 class SDRAMCore(Module, AutoCSR):

misoc/mem/sdram/core/lasmicon/__init__.py

@@ -1,10 +1,10 @@
 from migen.fhdl.std import *
 
-from misoclib.mem.sdram.phy import dfi
-from misoclib.mem.sdram.core import lasmibus
-from misoclib.mem.sdram.core.lasmicon.refresher import *
-from misoclib.mem.sdram.core.lasmicon.bankmachine import *
-from misoclib.mem.sdram.core.lasmicon.multiplexer import *
+from misoc.mem.sdram.phy import dfi
+from misoc.mem.sdram.core import lasmibus
+from misoc.mem.sdram.core.lasmicon.refresher import *
+from misoc.mem.sdram.core.lasmicon.bankmachine import *
+from misoc.mem.sdram.core.lasmicon.multiplexer import *
 
 
 class LASMIconSettings:

misoc/mem/sdram/core/lasmicon/bankmachine.py

@@ -4,7 +4,7 @@ from migen.genlib.fsm import FSM, NextState
 from migen.genlib.misc import optree
 from migen.genlib.fifo import SyncFIFO
 
-from misoclib.mem.sdram.core.lasmicon.multiplexer import *
+from misoc.mem.sdram.core.lasmicon.multiplexer import *
 
 
 class _AddressSlicer:

misoc/mem/sdram/core/lasmicon/multiplexer.py

@@ -4,7 +4,7 @@ from migen.genlib.misc import optree
 from migen.genlib.fsm import FSM, NextState
 from migen.bank.description import AutoCSR
 
-from misoclib.mem.sdram.core.lasmicon.perf import Bandwidth
+from misoc.mem.sdram.core.lasmicon.perf import Bandwidth
 
 
 class CommandRequest:

misoc/mem/sdram/core/lasmicon/refresher.py

@@ -2,7 +2,7 @@ from migen.fhdl.std import *
 from migen.genlib.misc import timeline
 from migen.genlib.fsm import FSM
 
-from misoclib.mem.sdram.core.lasmicon.multiplexer import *
+from misoc.mem.sdram.core.lasmicon.multiplexer import *
 
 
 class Refresher(Module):

misoc/mem/sdram/core/lasmixbar.py

@@ -3,7 +3,7 @@ from migen.genlib import roundrobin
 from migen.genlib.record import *
 from migen.genlib.misc import optree
 
-from misoclib.mem.sdram.core.lasmibus import Interface
+from misoc.mem.sdram.core.lasmibus import Interface
 
 
 def _getattr_all(l, attr):

misoc/mem/sdram/core/minicon/__init__.py

@@ -3,7 +3,7 @@ from migen.bus import wishbone
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.misc import optree, WaitTimer
 
-from misoclib.mem.sdram.phy import dfi as dfibus
+from misoc.mem.sdram.phy import dfi as dfibus
 
 
 class _AddressSlicer:

misoc/mem/sdram/frontend/memtest.py

@@ -3,7 +3,7 @@ from migen.genlib.misc import optree
 from migen.bank.description import *
 from migen.actorlib.spi import *
 
-from misoclib.mem.sdram.frontend import dma_lasmi
+from misoc.mem.sdram.frontend import dma_lasmi
 
 
 @DecorateModule(InsertReset)

misoc/mem/sdram/module.py

@@ -17,7 +17,7 @@
 from math import ceil
 
 from migen.fhdl.std import *
-from misoclib.mem import sdram
+from misoc.mem import sdram
 
 
 class SDRAMModule:

misoc/mem/sdram/phy/dfii.py

@@ -1,7 +1,7 @@
 from migen.fhdl.std import *
 from migen.bank.description import *
 
-from misoclib.mem.sdram.phy import dfi
+from misoc.mem.sdram.phy import dfi
 
 
 class PhaseInjector(Module, AutoCSR):

misoc/mem/sdram/phy/gensdrphy.py

@@ -25,8 +25,8 @@ from migen.fhdl.std import *
 from migen.genlib.record import *
 from migen.fhdl.specials import *
 
-from misoclib.mem.sdram.phy.dfi import *
-from misoclib.mem import sdram
+from misoc.mem.sdram.phy.dfi import *
+from misoc.mem import sdram
 
 
 class GENSDRPHY(Module):

misoc/mem/sdram/phy/k7ddrphy.py

@@ -3,8 +3,8 @@
 from migen.fhdl.std import *
 from migen.bank.description import *
 
-from misoclib.mem.sdram.phy.dfi import *
-from misoclib.mem import sdram
+from misoc.mem.sdram.phy.dfi import *
+from misoc.mem import sdram
 
 
 class K7DDRPHY(Module, AutoCSR):

misoc/mem/sdram/phy/s6ddrphy.py

@@ -19,8 +19,8 @@
 from migen.fhdl.std import *
 from migen.genlib.record import *
 
-from misoclib.mem.sdram.phy.dfi import *
-from misoclib.mem import sdram
+from misoc.mem.sdram.phy.dfi import *
+from misoc.mem import sdram
 
 
 class S6HalfRateDDRPHY(Module):

misoc/mem/sdram/phy/simphy.py

@@ -8,8 +8,8 @@
 
 from migen.fhdl.std import *
 from migen.fhdl.specials import *
-from misoclib.mem.sdram.phy.dfi import *
-from misoclib.mem import sdram
+from misoc.mem.sdram.phy.dfi import *
+from misoc.mem import sdram
 
 
 class Bank(Module):

misoc/mem/sdram/test/abstract_transactions_lasmi.py

@@ -2,7 +2,7 @@ from migen.fhdl.std import *
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.core import lasmibus
+from misoc.mem.sdram.core import lasmibus
 
 
 def my_generator(n):

misoc/mem/sdram/test/bankmachine_tb.py

@@ -1,8 +1,8 @@
 from migen.fhdl.std import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.code import lasmibus
-from misoclib.mem.sdram.core.lasmicon.bankmachine import *
+from misoc.mem.sdram.code import lasmibus
+from misoc.mem.sdram.core.lasmicon.bankmachine import *
 
 from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger
 

misoc/mem/sdram/test/common.py

@@ -3,7 +3,7 @@ from math import ceil
 
 from migen.fhdl.std import *
 
-from misoclib import sdram
+from misoc import sdram
 
 MHz = 1000000
 clk_freq = (83 + Fraction(1, 3))*MHz

misoc/mem/sdram/test/lasmicon_df_tb.py

@@ -1,9 +1,9 @@
 from migen.fhdl.std import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.core import lasmibus
-from misoclib.mem.sdram.core.lasmicon import *
-from misoclib.mem.sdram.frontend import dma_lasmi
+from misoc.mem.sdram.core import lasmibus
+from misoc.mem.sdram.core.lasmicon import *
+from misoc.mem.sdram.frontend import dma_lasmi
 
 from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
 

misoc/mem/sdram/test/lasmicon_tb.py

@@ -1,8 +1,8 @@
 from migen.fhdl.std import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.core import lasmibus
-from misoclib.mem.sdram.core.lasmicon import *
+from misoc.mem.sdram.core import lasmibus
+from misoc.mem.sdram.core.lasmicon import *
 
 from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
 

misoc/mem/sdram/test/lasmicon_wb.py

@@ -3,9 +3,9 @@ from migen.bus import wishbone
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.core import lasmibus
-from misoclib.mem.sdram.core.lasmicon import *
-from misoclib.mem.sdram.frontend import wishbone2lasmi
+from misoc.mem.sdram.core import lasmibus
+from misoc.mem.sdram.core.lasmicon import *
+from misoc.mem.sdram.frontend import wishbone2lasmi
 
 from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
 

misoc/mem/sdram/test/minicon_tb.py

@@ -4,9 +4,9 @@ from migen.bus import wishbone
 from migen.sim.generic import Simulator
 from migen.sim import icarus
 from mibuild.platforms import papilio_pro as board
-from misoclib import sdram
-from misoclib.mem.sdram.core.minicon import Minicon
-from misoclib.mem.sdram.phy import gensdrphy
+from misoc import sdram
+from misoc.mem.sdram.core.minicon import Minicon
+from misoc.mem.sdram.phy import gensdrphy
 from itertools import chain
 from os.path import isfile
 import sys

misoc/mem/sdram/test/refresher.py

@@ -3,7 +3,7 @@ from random import Random
 from migen.fhdl.std import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.core.lasmicon.refresher import *
+from misoc.mem.sdram.core.lasmicon.refresher import *
 
 from common import CommandLogger
 

misoc/soc/__init__.py

@@ -4,10 +4,10 @@ from migen.fhdl.std import *
 from migen.bank import csrgen
 from migen.bus import wishbone, csr, wishbone2csr
 
-from misoclib.com.uart.phy import UARTPHY
-from misoclib.com import uart
-from misoclib.cpu import lm32, mor1kx
-from misoclib.cpu import identifier, timer
+from misoc.com.uart.phy import UARTPHY
+from misoc.com import uart
+from misoc.cpu import lm32, mor1kx
+from misoc.cpu import identifier, timer
 
 
 def mem_decoder(address, start=26, end=29):

misoc/soc/sdram.py

@@ -2,11 +2,11 @@ from migen.fhdl.std import *
 from migen.bus import wishbone
 from migen.genlib.record import *
 
-from misoclib.mem.sdram.core import SDRAMCore
-from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
-from misoclib.mem.sdram.core.minicon import MiniconSettings
-from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi
-from misoclib.soc import SoC
+from misoc.mem.sdram.core import SDRAMCore
+from misoc.mem.sdram.core.lasmicon import LASMIconSettings
+from misoc.mem.sdram.core.minicon import MiniconSettings
+from misoc.mem.sdram.frontend import memtest, wishbone2lasmi
+from misoc.soc import SoC
 
 
 class SDRAMSoC(SoC):

misoc/video/dvisampler/__init__.py

@@ -1,15 +1,15 @@
 from migen.fhdl.std import *
 from migen.bank.description import AutoCSR
 
-from misoclib.video.dvisampler.edid import EDID
-from misoclib.video.dvisampler.clocking import Clocking
-from misoclib.video.dvisampler.datacapture import DataCapture
-from misoclib.video.dvisampler.charsync import CharSync
-from misoclib.video.dvisampler.wer import WER
-from misoclib.video.dvisampler.decoding import Decoding
-from misoclib.video.dvisampler.chansync import ChanSync
-from misoclib.video.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
-from misoclib.video.dvisampler.dma import DMA
+from misoc.video.dvisampler.edid import EDID
+from misoc.video.dvisampler.clocking import Clocking
+from misoc.video.dvisampler.datacapture import DataCapture
+from misoc.video.dvisampler.charsync import CharSync
+from misoc.video.dvisampler.wer import WER
+from misoc.video.dvisampler.decoding import Decoding
+from misoc.video.dvisampler.chansync import ChanSync
+from misoc.video.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
+from misoc.video.dvisampler.dma import DMA
 
 
 class DVISampler(Module, AutoCSR):

misoc/video/dvisampler/analysis.py

@@ -5,7 +5,7 @@ from migen.genlib.record import Record
 from migen.bank.description import *
 from migen.flow.actor import *
 
-from misoclib.video.dvisampler.common import channel_layout
+from misoc.video.dvisampler.common import channel_layout
 
 
 class SyncPolarity(Module):

misoc/video/dvisampler/chansync.py

@@ -5,7 +5,7 @@ from migen.genlib.record import Record, layout_len
 from migen.genlib.misc import optree
 from migen.bank.description import *
 
-from misoclib.video.dvisampler.common import channel_layout
+from misoc.video.dvisampler.common import channel_layout
 
 
 class _SyncBuffer(Module):

misoc/video/dvisampler/charsync.py

@@ -3,7 +3,7 @@ from migen.genlib.cdc import MultiReg
 from migen.genlib.misc import optree
 from migen.bank.description import *
 
-from misoclib.video.dvisampler.common import control_tokens
+from misoc.video.dvisampler.common import control_tokens
 
 
 class CharSync(Module, AutoCSR):

misoc/video/dvisampler/debug.py

@@ -4,10 +4,10 @@ from migen.genlib.record import layout_len
 from migen.bank.description import AutoCSR
 from migen.actorlib import structuring, spi
 
-from misoclib.mem.sdram.frontend import dma_lasmi
-from misoclib.video.dvisampler.edid import EDID
-from misoclib.video.dvisampler.clocking import Clocking
-from misoclib.video.dvisampler.datacapture import DataCapture
+from misoc.mem.sdram.frontend import dma_lasmi
+from misoc.video.dvisampler.edid import EDID
+from misoc.video.dvisampler.clocking import Clocking
+from misoc.video.dvisampler.datacapture import DataCapture
 
 
 class RawDVISampler(Module, AutoCSR):

misoc/video/dvisampler/decoding.py

@@ -1,7 +1,7 @@
 from migen.fhdl.std import *
 from migen.genlib.record import Record
 
-from misoclib.video.dvisampler.common import control_tokens, channel_layout
+from misoc.video.dvisampler.common import control_tokens, channel_layout
 
 
 class Decoding(Module):

misoc/video/dvisampler/dma.py

@@ -4,7 +4,7 @@ from migen.bank.description import *
 from migen.bank.eventmanager import *
 from migen.flow.actor import *
 
-from misoclib.mem.sdram.frontend import dma_lasmi
+from misoc.mem.sdram.frontend import dma_lasmi
 
 
 # Slot status: EMPTY=0 LOADED=1 PENDING=2

misoc/video/dvisampler/wer.py

@@ -3,7 +3,7 @@ from migen.bank.description import *
 from migen.genlib.misc import optree
 from migen.genlib.cdc import PulseSynchronizer
 
-from misoclib.video.dvisampler.common import control_tokens
+from misoc.video.dvisampler.common import control_tokens
 
 
 class WER(Module, AutoCSR):

misoc/video/framebuffer/__init__.py

@@ -4,9 +4,9 @@ from migen.flow import plumbing
 from migen.bank.description import AutoCSR
 from migen.actorlib import structuring, misc
 
-from misoclib.mem.sdram.frontend import dma_lasmi
-from misoclib.video.framebuffer.format import bpp, pixel_layout, FrameInitiator, VTG
-from misoclib.video.framebuffer.phy import Driver
+from misoc.mem.sdram.frontend import dma_lasmi
+from misoc.video.framebuffer.format import bpp, pixel_layout, FrameInitiator, VTG
+from misoc.video.framebuffer.phy import Driver
 
 
 class Framebuffer(Module, AutoCSR):

misoc/video/framebuffer/phy.py

@@ -4,8 +4,8 @@ from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 from migen.flow.actor import *
 
-from misoclib.video.framebuffer.format import bpc_phy, phy_layout
-from misoclib.video.framebuffer import dvi
+from misoc.video.framebuffer.format import bpc_phy, phy_layout
+from misoc.video.framebuffer import dvi
 
 
 class _FIFO(Module):

setup.py

@@ -1,38 +1,38 @@
-#!/usr/bin/env python3
-
-import sys
-import os
-from setuptools import setup
-from setuptools import find_packages
-
-here = os.path.abspath(os.path.dirname(__file__))
-README = open(os.path.join(here, "README")).read()
-
-required_version = (3, 3)
-if sys.version_info < required_version:
-    raise SystemExit("MiSoC requires python {0} or greater".format(
-        ".".join(map(str, required_version))))
-
-setup(
-    name="misoclib",
-    version="unknown",
-    description="a high performance and small footprint SoC based on Migen",
-    long_description=README,
-    author="Sebastien Bourdeauducq",
-    author_email="sb@m-labs.hk",
-    url="http://m-labs.hk",
-    download_url="https://github.com/m-labs/misoc",
-    packages=find_packages(here),
-    license="BSD",
-    platforms=["Any"],
-    keywords="HDL ASIC FPGA hardware design",
-    classifiers=[
-        "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
-        "Environment :: Console",
-        "Development Status :: Alpha",
-        "Intended Audience :: Developers",
-        "License :: OSI Approved :: BSD License",
-        "Operating System :: OS Independent",
-        "Programming Language :: Python",
-    ],
-)
+#!/usr/bin/env python3
+
+import sys
+import os
+from setuptools import setup
+from setuptools import find_packages
+
+here = os.path.abspath(os.path.dirname(__file__))
+README = open(os.path.join(here, "README")).read()
+
+required_version = (3, 3)
+if sys.version_info < required_version:
+    raise SystemExit("MiSoC requires python {0} or greater".format(
+        ".".join(map(str, required_version))))
+
+setup(
+    name="misoc",
+    version="unknown",
+    description="a high performance and small footprint SoC based on Migen",
+    long_description=README,
+    author="Sebastien Bourdeauducq",
+    author_email="sb@m-labs.hk",
+    url="http://m-labs.hk",
+    download_url="https://github.com/m-labs/misoc",
+    packages=find_packages(here),
+    license="BSD",
+    platforms=["Any"],
+    keywords="HDL ASIC FPGA hardware design",
+    classifiers=[
+        "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
+        "Environment :: Console",
+        "Development Status :: Alpha",
+        "Intended Audience :: Developers",
+        "License :: OSI Approved :: BSD License",
+        "Operating System :: OS Independent",
+        "Programming Language :: Python",
+    ],
+)