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build/vhd2v_converter.py: fix params vs instance when conversion is disabled

This commit is contained in:
Gwenhael Goavec-Merou 2024-12-19 17:59:58 +01:00
parent 6228d2b024
commit 8254a349f8
1 changed files with 4 additions and 1 deletions
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litex/build/vhd2v_converter.py
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@ -138,7 +138,10 @@ class VHD2VConverter(Module):
# platform able to synthesis verilog and vhdl -> no conversion # platform able to synthesis verilog and vhdl -> no conversion
if self._platform.support_mixed_language and not self._force_convert: if self._platform.support_mixed_language and not self._force_convert:
ip_params = self._params if self._params:
ip_params = self._params
else:
ip_params = self._instance.items
for file in self._sources: for file in self._sources:
self._platform.add_source(file, library=self._work_package) self._platform.add_source(file, library=self._work_package)
else: # platform is only able to synthesis verilog -> convert vhdl to verilog else: # platform is only able to synthesis verilog -> convert vhdl to verilog