add CSV CSR map output
This commit is contained in:
Sebastien Bourdeauducq
parent
1672c4a176
commit
833d7c7eec
16
make.py
16
make.py
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@ -4,10 +4,11 @@ import argparse, os, importlib, subprocess
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from mibuild.tools import write_to_file
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from milkymist import cif
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from milkymist import cpuif
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from milkymist.s6ddrphy import initsequence
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import top, jtag
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def build(platform_name, build_bitstream, build_header, *soc_args, **soc_kwargs):
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def build(platform_name, build_bitstream, build_header, csr_csv_filename, *soc_args, **soc_kwargs):
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platform_module = importlib.import_module("mibuild.platforms."+platform_name)
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platform = platform_module.Platform()
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soc = top.SoC(platform, platform_name, *soc_args, **soc_kwargs)
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@ -46,24 +47,27 @@ TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
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else:
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soc.finalize()
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if build_header:
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csr_header = cif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
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csr_header = cpuif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
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write_to_file("software/include/hw/csr.h", csr_header)
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sdram_phy_header = cif.get_sdram_phy_header(soc.ddrphy)
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sdram_phy_header = initsequence.get_sdram_phy_header(soc.ddrphy)
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write_to_file("software/include/hw/sdram_phy.h", sdram_phy_header)
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if csr_csv_filename:
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csr_csv = cpuif.get_csr_csv(soc.csr_base, soc.csrbankarray)
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write_to_file(csr_csv_filename, csr_csv)
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def main():
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parser = argparse.ArgumentParser(description="milkymist-ng - a high performance SoC built on Migen technology.")
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parser.add_argument("-p", "--platform", default="mixxeo", help="platform to build for")
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parser.add_argument("-B", "--no-bitstream", default=False, action="store_true", help="do not build bitstream file")
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parser.add_argument("-H", "--no-header", default=False, action="store_true", help="do not build C header files with CSR/IRQ/SDRAM_PHY defs")
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parser.add_argument("-c", "--csr-csv", default="", help="save CSR map in CSV file")
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parser.add_argument("-l", "--load", default=False, action="store_true", help="load bitstream to SRAM")
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parser.add_argument("-f", "--flash", default=False, action="store_true", help="load bitstream to flash")
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parser.add_argument("-m", "--with-memtest", default=False, action="store_true", help="include memtest cores")
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args = parser.parse_args()
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build(args.platform, not args.no_bitstream, not args.no_header, args.with_memtest)
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build(args.platform, not args.no_bitstream, not args.no_header, args.csr_csv, args.with_memtest)
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if args.load:
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jtag.load("build/soc-"+args.platform+".bit")
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if args.flash:
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@ -0,0 +1,64 @@
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from migen.bank.description import CSRStatus
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def _get_rw_functions(reg_name, reg_base, size, read_only):
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r = ""
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if size > 8:
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raise NotImplementedError("Register too large")
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elif size > 4:
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ctype = "unsigned long long int"
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elif size > 2:
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ctype = "unsigned int"
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elif size > 1:
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ctype = "unsigned short int"
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else:
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ctype = "unsigned char"
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r += "static inline "+ctype+" "+reg_name+"_read(void) {\n"
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if size > 1:
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r += "\t"+ctype+" r = MMPTR("+hex(reg_base)+");\n"
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for byte in range(1, size):
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r += "\tr <<= 8;\n\tr |= MMPTR("+hex(reg_base+4*byte)+");\n"
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r += "\treturn r;\n}\n"
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else:
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r += "\treturn MMPTR("+hex(reg_base)+");\n}\n"
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if not read_only:
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r += "static inline void "+reg_name+"_write("+ctype+" value) {\n"
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for byte in range(size):
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shift = (size-byte-1)*8
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if shift:
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value_shifted = "value >> "+str(shift)
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else:
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value_shifted = "value"
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r += "\tMMPTR("+hex(reg_base+4*byte)+") = "+value_shifted+";\n"
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r += "}\n"
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return r
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def get_csr_header(csr_base, bank_array, interrupt_map):
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r = "#ifndef __HW_CSR_H\n#define __HW_CSR_H\n#include <hw/common.h>\n"
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for name, csrs, mapaddr, rmap in bank_array.banks:
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r += "\n/* "+name+" */\n"
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reg_base = csr_base + 0x800*mapaddr
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r += "#define "+name.upper()+"_BASE "+hex(reg_base)+"\n"
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for csr in csrs:
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nr = (csr.size + 7)//8
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r += _get_rw_functions(name + "_" + csr.name, reg_base, nr, isinstance(csr, CSRStatus))
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reg_base += 4*nr
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try:
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interrupt_nr = interrupt_map[name]
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except KeyError:
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pass
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else:
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r += "#define "+name.upper()+"_INTERRUPT "+str(interrupt_nr)+"\n"
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r += "\n#endif\n"
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return r
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def get_csr_csv(csr_base, bank_array):
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r = ""
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for name, csrs, mapaddr, rmap in bank_array.banks:
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reg_base = csr_base + 0x800*mapaddr
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for csr in csrs:
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nr = (csr.size + 7)//8
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r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, reg_base, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
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reg_base += 4*nr
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return r
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@ -1,70 +1,4 @@
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from operator import itemgetter
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import re
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from migen.fhdl.std import *
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from migen.bank.description import CSRStatus
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def get_macros(filename):
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f = open(filename, "r")
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r = {}
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for line in f:
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match = re.match("\w*#define\s+(\w+)\s+(.*)", line, re.IGNORECASE)
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if match:
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r[match.group(1)] = match.group(2)
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return r
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def _get_rw_functions(reg_name, reg_base, size, read_only):
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r = ""
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if size > 8:
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raise NotImplementedError("Register too large")
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elif size > 4:
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ctype = "unsigned long long int"
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elif size > 2:
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ctype = "unsigned int"
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elif size > 1:
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ctype = "unsigned short int"
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else:
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ctype = "unsigned char"
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r += "static inline "+ctype+" "+reg_name+"_read(void) {\n"
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if size > 1:
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r += "\t"+ctype+" r = MMPTR("+hex(reg_base)+");\n"
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for byte in range(1, size):
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r += "\tr <<= 8;\n\tr |= MMPTR("+hex(reg_base+4*byte)+");\n"
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r += "\treturn r;\n}\n"
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else:
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r += "\treturn MMPTR("+hex(reg_base)+");\n}\n"
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if not read_only:
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r += "static inline void "+reg_name+"_write("+ctype+" value) {\n"
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for byte in range(size):
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shift = (size-byte-1)*8
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if shift:
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value_shifted = "value >> "+str(shift)
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else:
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value_shifted = "value"
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r += "\tMMPTR("+hex(reg_base+4*byte)+") = "+value_shifted+";\n"
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r += "}\n"
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return r
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def get_csr_header(csr_base, bank_array, interrupt_map):
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r = "#ifndef __HW_CSR_H\n#define __HW_CSR_H\n#include <hw/common.h>\n"
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for name, csrs, mapaddr, rmap in bank_array.banks:
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r += "\n/* "+name+" */\n"
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reg_base = csr_base + 0x800*mapaddr
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r += "#define "+name.upper()+"_BASE "+hex(reg_base)+"\n"
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for csr in csrs:
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nr = (csr.size + 7)//8
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r += _get_rw_functions(name + "_" + csr.name, reg_base, nr, isinstance(csr, CSRStatus))
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reg_base += 4*nr
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try:
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interrupt_nr = interrupt_map[name]
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except KeyError:
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pass
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else:
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r += "#define "+name.upper()+"_INTERRUPT "+str(interrupt_nr)+"\n"
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r += "\n#endif\n"
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return r
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from migen.fhdl.std import log2_int
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def get_sdram_phy_header(sdram_phy):
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if sdram_phy.phy_settings.memtype not in ["SDR", "DDR", "LPDDR", "DDR2"]:
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3
top.py
3
top.py
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@ -10,9 +10,8 @@ from mibuild.generic_platform import ConstraintError
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from milkymist import mxcrg, lm32, norflash, uart, s6ddrphy, dfii, lasmicon, \
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identifier, timer, minimac3, framebuffer, dvisampler, gpio, memtest
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from milkymist.cif import get_macros
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version = get_macros("common/version.h")["VERSION"][1:-1]
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version = "2.0"
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clk_freq = (83 + Fraction(1, 3))*1000000
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sram_size = 4096 # in bytes
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