cores/xadc: Re-arrange and simplify code a bit.
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@ -5,31 +5,41 @@
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# SPDX-License-Identifier: BSD-2-Clause
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import math
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from migen import *
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from migen import *
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from litex.gen import *
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect.csr import *
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# Xilinx DNA (Device Identifier) -------------------------------------------------------------------
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# Xilinx DNA (Device Identifier) -------------------------------------------------------------------
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class DNA(Module, AutoCSR):
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class XilinxDNA(Module, AutoCSR):
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nbits = 57
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def __init__(self, nbits=57, primitive="DNA_PORT", clk_divider=16):
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def __init__(self):
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self.nbits = nbits
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self._id = CSRStatus(self.nbits)
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self.clk_divider = clk_divider
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self._id = CSRStatus(nbits)
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# # #
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# # #
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# Create slow DNA Clk (sys_clk/16).
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# Parameters check.
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assert nbits <= 256
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assert clk_divider > 1
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assert math.log2(clk_divider).is_integer()
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# Create slow DNA Clk.
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self.clock_domains.cd_dna = ClockDomain()
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self.clock_domains.cd_dna = ClockDomain()
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dna_clk_count = Signal(4)
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dna_clk_count = Signal(int(math.log2(clk_divider)))
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self.sync += dna_clk_count.eq(dna_clk_count + 1)
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self.sync += dna_clk_count.eq(dna_clk_count + 1)
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self.sync += self.cd_dna.clk.eq(dna_clk_count[3])
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self.sync += self.cd_dna.clk.eq(dna_clk_count[-1])
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# Shift-Out DNA Identifier.
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# Shift-Out DNA Identifier.
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count = Signal(8)
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count = Signal(8)
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dout = Signal()
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dout = Signal()
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self.specials += Instance("DNA_PORT",
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self.specials += Instance(primitive,
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i_CLK = ClockSignal("dna"),
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i_CLK = ClockSignal("dna"),
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i_READ = (count == 0),
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i_READ = (count == 0),
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i_SHIFT = 1,
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i_SHIFT = 1,
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@ -37,12 +47,20 @@ class DNA(Module, AutoCSR):
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o_DOUT = dout,
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o_DOUT = dout,
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)
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)
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self.sync.dna += [
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self.sync.dna += [
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If(count < (self.nbits + 1),
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If(count < (nbits + 1),
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count.eq(count + 1),
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count.eq(count + 1),
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self._id.status.eq(Cat(dout, self._id.status))
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self._id.status.eq(Cat(dout, self._id.status))
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)
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)
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]
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]
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def add_timing_constraints(self, platform, sys_clk_freq, sys_clk):
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def add_timing_constraints(self, platform, sys_clk_freq, sys_clk):
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platform.add_period_constraint(self.cd_dna.clk, 16*1e9/sys_clk_freq)
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platform.add_period_constraint(self.cd_dna.clk, self.clk_divider*1e9/sys_clk_freq)
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platform.add_false_path_constraints(self.cd_dna.clk, sys_clk)
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platform.add_false_path_constraints(self.cd_dna.clk, sys_clk)
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# Xilinx 7-Series DNA ------------------------------------------------------------------------------
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class S7DNA(XilinxDNA):
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def __init__(self, *args, **kwargs):
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XilinxDNA.__init__(self, nbits=57, primitive="DNA_PORT", *args, **kwargs)
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class DNA(XilinxDNA): pass # Compat.
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