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SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets

This commit is contained in:
Florent Kermarrec 2020-01-13 14:59:17 +01:00
parent 6e3f25a7e0
commit 83a7225ccc
14 changed files with 36 additions and 70 deletions
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9
litex/boards/targets/arty.py
View File

@ -48,14 +48,11 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = arty.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
**kwargs)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -81,7 +78,7 @@ class EthernetSoC(BaseSoC):
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))

4
litex/boards/targets/de0nano.py
View File

@ -76,9 +76,7 @@ class BaseSoC(SoCSDRAM):
platform = de0nano.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform)

9
litex/boards/targets/genesys2.py
View File

@ -41,14 +41,11 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
platform = genesys2.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size = integrated_rom_size,
integrated_sram_size = 0x8000,
**kwargs)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -74,7 +71,7 @@ class EthernetSoC(BaseSoC):
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))

9
litex/boards/targets/kc705.py
View File

@ -43,14 +43,11 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
platform = kc705.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size = integrated_rom_size,
integrated_sram_size = 0x8000,
**kwargs)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -76,7 +73,7 @@ class EthernetSoC(BaseSoC):
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"),
self.platform.request("eth"), clk_freq=self.clk_freq)

7
litex/boards/targets/kcu105.py
View File

@ -81,10 +81,7 @@ class BaseSoC(SoCSDRAM):
platform = kcu105.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size = integrated_rom_size,
integrated_sram_size = 0x8000,
**kwargs)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -111,7 +108,7 @@ class EthernetSoC(BaseSoC):
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
BaseSoC.__init__(self, **kwargs)
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,

4
litex/boards/targets/minispartan6.py
View File

@ -49,9 +49,7 @@ class BaseSoC(SoCSDRAM):
platform = minispartan6.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size = 0x8000,
**kwargs)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

9
litex/boards/targets/netv2.py
View File

@ -46,14 +46,11 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = netv2.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size = integrated_rom_size,
integrated_sram_size = 0x8000,
**kwargs)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -79,7 +76,7 @@ class EthernetSoC(BaseSoC):
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))

7
litex/boards/targets/nexys4ddr.py
View File

@ -45,14 +45,11 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = nexys4ddr.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size = integrated_rom_size,
integrated_sram_size = 0x8000,
**kwargs)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

9
litex/boards/targets/nexys_video.py
View File

@ -45,14 +45,11 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = nexys_video.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size = integrated_rom_size,
integrated_sram_size = 0x8000,
**kwargs)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -78,7 +75,7 @@ class EthernetSoC(BaseSoC):
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))

7
litex/boards/targets/pcie_screamer.py
View File

@ -39,14 +39,11 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = pcie_screamer.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
**kwargs)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

10
litex/boards/targets/simple.py
View File

@ -19,14 +19,12 @@ from liteeth.mac import LiteEthMAC
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, platform, integrated_rom_size=0x8000, **kwargs):
def __init__(self, platform, **kwargs):
sys_clk_freq = int(1e9/platform.default_clk_period)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
integrated_main_ram_size=16*1024,
**kwargs)
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
@ -38,7 +36,7 @@ class EthernetSoC(BaseSoC):
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, platform, integrated_rom_size=0x10000, **kwargs):
def __init__(self, platform, **kwargs):
BaseSoC.__init__(self, platform, **kwargs)
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),

4
litex/boards/targets/ulx3s.py
View File

@ -55,9 +55,7 @@ class BaseSoC(SoCSDRAM):
sys_clk_freq = int(50e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

8
litex/boards/targets/versa_ecp5.py
View File

@ -72,13 +72,11 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs):
def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
**kwargs)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -105,7 +103,7 @@ class EthernetSoC(BaseSoC):
mem_map.update(BaseSoC.mem_map)
def __init__(self, toolchain="diamond", **kwargs):
BaseSoC.__init__(self, toolchain=toolchain, integrated_rom_size=0x10000, **kwargs)
BaseSoC.__init__(self, toolchain=toolchain, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(
self.platform.request("eth_clocks"),

10
litex/soc/integration/soc_core.py
View File

@ -85,7 +85,7 @@ class SoCCore(Module):
# CPU parameters
cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None,
# ROM parameters
integrated_rom_size=0, integrated_rom_init=[],
integrated_rom_size=32768, integrated_rom_init=[],
# SRAM parameters
integrated_sram_size=4096, integrated_sram_init=[],
# MAIN_RAM parameters
@ -560,13 +560,13 @@ def soc_core_args(parser):
parser.add_argument("--cpu-reset-address", default=None, type=int,
help="CPU reset address (default=0x00000000 or ROM)")
# ROM parameters
parser.add_argument("--integrated-rom-size", default=None, type=int,
parser.add_argument("--integrated-rom-size", default=0x8000, type=int,
help="size/enable the integrated (BIOS) ROM")
parser.add_argument("--integrated-rom-file", default=None, type=str,
help="integrated (BIOS) ROM binary file")
help="integrated (BIOS) ROM binary file (default=32KB)")
# SRAM parameters
parser.add_argument("--integrated_sram_size", default=None,
help="size/enable the integrated SRAM")
parser.add_argument("--integrated_sram_size", default=0x1000,
help="size/enable the integrated SRAM (default=4KB)")
# MAIN_RAM parameters
parser.add_argument("--integrated-main-ram-size", default=None, type=int,
help="size/enable the integrated main RAM")