interconnect/axi: Add AXI version to AXIInterface (default to AXI4) and handle AXI3/AXI4 differences.
- Max burst length of 16 in AXI3, 256 in AXI4. - No WID in AXI4.
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@ -72,6 +72,8 @@ def connect_to_pads(bus, pads, mode="master", axi_full=False):
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if channel in ["w", "r"] and axi_full:
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if channel in ["w", "r"] and axi_full:
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sig_list += [("last", 1)]
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sig_list += [("last", 1)]
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for name, width in sig_list:
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for name, width in sig_list:
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if (channel == "w") and (name == "id") and (bus.version == "axi4"):
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continue # No WID on AXI4.
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sig = getattr(ch, name)
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sig = getattr(ch, name)
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pad = getattr(pads, channel + name)
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pad = getattr(pads, channel + name)
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if mode == "master":
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if mode == "master":
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@ -19,12 +19,13 @@ from litex.soc.interconnect.axi.axi_stream import AXIStreamInterface
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# AXI Definition -----------------------------------------------------------------------------------
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# AXI Definition -----------------------------------------------------------------------------------
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def ax_description(address_width):
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def ax_description(address_width, version="axi4"):
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len_width = {"axi3":4, "axi4":8}[version]
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# * present for interconnect with others cores but not used by LiteX.
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# * present for interconnect with others cores but not used by LiteX.
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return [
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return [
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("addr", address_width), # Address Width.
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("addr", address_width), # Address Width.
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("burst", 2), # Burst type.
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("burst", 2), # Burst type.
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("len", 8), # Number of data (-1) transfers (up to 256).
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("len", len_width), # Number of data (-1) transfers (up to 16 (AXI3) or 256 (AXI4)).
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("size", 4), # Number of bytes (-1) of each data transfer (up to 1024 bits).
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("size", 4), # Number of bytes (-1) of each data transfer (up to 1024 bits).
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("lock", 2), # *
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("lock", 2), # *
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("prot", 3), # *
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("prot", 3), # *
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@ -49,30 +50,39 @@ def r_description(data_width):
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]
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]
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class AXIInterface:
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class AXIInterface:
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def __init__(self, data_width=32, address_width=32, id_width=1, clock_domain="sys", name=None, bursting=False,
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def __init__(self, data_width=32, address_width=32, id_width=1, version="axi4", clock_domain="sys",
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name = None,
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bursting = False,
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aw_user_width = 0,
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aw_user_width = 0,
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w_user_width = 0,
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w_user_width = 0,
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b_user_width = 0,
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b_user_width = 0,
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ar_user_width = 0,
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ar_user_width = 0,
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r_user_width = 0
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r_user_width = 0
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):
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):
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# Parameters checks.
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# ------------------
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assert data_width in [32, 64, 128, 256, 512, 1024]
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assert version in ["axi3", "axi4"]
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# Parameters.
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# Parameters.
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# -----------
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self.data_width = data_width
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self.data_width = data_width
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self.address_width = address_width
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self.address_width = address_width
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self.id_width = id_width
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self.id_width = id_width
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self.version = version
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self.clock_domain = clock_domain
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self.clock_domain = clock_domain
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self.bursting = bursting # FIXME: Use or add check.
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self.bursting = bursting # FIXME: Use or add check.
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# Write Channels.
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# Write Channels.
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# ---------------
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# ---------------
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self.aw = AXIStreamInterface(name=name,
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self.aw = AXIStreamInterface(name=name,
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layout = ax_description(address_width),
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layout = ax_description(address_width=address_width, version=version),
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id_width = id_width,
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id_width = id_width,
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user_width = aw_user_width
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user_width = aw_user_width
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)
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)
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self.w = AXIStreamInterface(name=name,
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self.w = AXIStreamInterface(name=name,
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layout = w_description(data_width),
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layout = w_description(data_width),
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id_width = id_width,
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id_width = {"axi3":0,"axi4":id_width}[version], # No WID on AXI4.
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user_width = w_user_width
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user_width = w_user_width
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)
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)
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self.b = AXIStreamInterface(name=name,
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self.b = AXIStreamInterface(name=name,
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@ -84,7 +94,7 @@ class AXIInterface:
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# Read Channels.
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# Read Channels.
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# --------------
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# --------------
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self.ar = AXIStreamInterface(name=name,
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self.ar = AXIStreamInterface(name=name,
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layout = ax_description(address_width),
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layout = ax_description(address_width=address_width, version=version),
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id_width = id_width,
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id_width = id_width,
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user_width = ar_user_width
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user_width = ar_user_width
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)
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)
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@ -108,6 +118,8 @@ class AXIInterface:
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channel_layout = (getattr(self, channel).description.payload_layout +
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channel_layout = (getattr(self, channel).description.payload_layout +
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getattr(self, channel).description.param_layout)
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getattr(self, channel).description.param_layout)
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for name, width in channel_layout:
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for name, width in channel_layout:
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if (channel == "w") and (name == "id") and (self.version == "axi4"):
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continue # No WID on AXI4.
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subsignals.append(Subsignal(channel + name, Pins(width)))
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subsignals.append(Subsignal(channel + name, Pins(width)))
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ios = [(bus_name , 0) + tuple(subsignals)]
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ios = [(bus_name , 0) + tuple(subsignals)]
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return ios
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return ios
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