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efinix: pll now force the generated clock into cd.clk *WARNING*

This commit is contained in:
Dolu1990 2024-09-05 10:16:43 +02:00
parent a90ab9dcca
commit 84e7e816c7
1 changed files with 6 additions and 2 deletions
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8
litex/soc/cores/clock/efinix.py
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@ -107,11 +107,15 @@ class EFINIXPLL(LiteXModule):
clk_out_name = f"{self.name}_clkout{self.nclkouts}" if name == "" else name clk_out_name = f"{self.name}_clkout{self.nclkouts}" if name == "" else name
if cd is not None: if cd is not None:
self.platform.add_extension([(clk_out_name, 0, Pins(1))])
clk_name = f"{cd.name}_clk" clk_name = f"{cd.name}_clk"
clk_out_name = clk_name # To unify constraints names
self.platform.add_extension([(clk_out_name, 0, Pins(1))])
clk_out = self.platform.request(clk_out_name) clk_out = self.platform.request(clk_out_name)
self.comb += cd.clk.eq(clk_out) self.comb += cd.clk.eq(clk_out)
self.platform.add_period_constraint(clk=clk_out, period=1e9/freq, name=clk_name) # Efinity will generate xxx.pt.sdc constraints automaticaly,
# so, the user realy need to use the toplevel pin from the pll instead of an intermediate signal
# This is a dirty workaround. But i don't have any better
cd.clk = clk_out
if with_reset: if with_reset:
self.specials += AsyncResetSynchronizer(cd, ~self.locked) self.specials += AsyncResetSynchronizer(cd, ~self.locked)
self.platform.toolchain.excluded_ios.append(clk_out_name) self.platform.toolchain.excluded_ios.append(clk_out_name)