fhdl/verilog: Add larger separators.
This commit is contained in:
Florent Kermarrec
parent
5a2399b037
commit
84e8fd0f9e
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@ -27,7 +27,9 @@ from migen.fhdl.specials import Memory
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from litex.gen.fhdl.memory import memory_emit_verilog
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from litex.build.tools import generated_banner
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# Reserved Keywords -------------------------------------------------------------------------------
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# ------------------------------------------------------------------------------------------------ #
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# RESERVED KEYWORDS #
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# ------------------------------------------------------------------------------------------------ #
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_ieee_1800_2017_verilog_reserved_keywords = {
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"accept_on", "alias", "always", "always_comb", "always_ff",
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@ -82,14 +84,9 @@ _ieee_1800_2017_verilog_reserved_keywords = {
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"wor", "xnor", "xor",
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}
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# Print Signal -------------------------------------------------------------------------------------
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def _print_signal(ns, s):
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return "{signed}{vector}{name}".format(
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signed = "" if (not s.signed) else "signed ",
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vector = "" if ( len(s) <= 1) else f"[{str(len(s)-1) }:0] ",
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name = ns.get_name(s)
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)
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# ------------------------------------------------------------------------------------------------ #
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# EXPRESSIONS #
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# ------------------------------------------------------------------------------------------------ #
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# Print Constant -----------------------------------------------------------------------------------
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@ -100,6 +97,15 @@ def _print_constant(node):
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value = abs(node.value),
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), node.signed
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# Print Signal -------------------------------------------------------------------------------------
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def _print_signal(ns, s):
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return "{signed}{vector}{name}".format(
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signed = "" if (not s.signed) else "signed ",
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vector = "" if ( len(s) <= 1) else f"[{str(len(s)-1) }:0] ",
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name = ns.get_name(s)
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)
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# Print Operator -----------------------------------------------------------------------------------
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(UNARY, BINARY, TERNARY) = (1, 2, 3)
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@ -209,14 +215,17 @@ def _print_expression(ns, node):
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else:
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raise TypeError(f"Expression of unrecognized type: '{type(node).__name__}'")
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# Print Node ---------------------------------------------------------------------------------------
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# ------------------------------------------------------------------------------------------------ #
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# NODES #
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# ------------------------------------------------------------------------------------------------ #
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(_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)
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def _print_node(ns, at, level, node, target_filter=None):
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if target_filter is not None and target_filter not in list_targets(node):
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return ""
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# Assignment.
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elif isinstance(node, _Assign):
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if at == _AT_BLOCKING:
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assignment = " = "
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@ -227,8 +236,12 @@ def _print_node(ns, at, level, node, target_filter=None):
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else:
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assignment = " <= "
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return "\t"*level + _print_expression(ns, node.l)[0] + assignment + _print_expression(ns, node.r)[0] + ";\n"
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# Iterable.
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elif isinstance(node, collections.abc.Iterable):
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return "".join(_print_node(ns, at, level, n, target_filter) for n in node)
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# If.
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elif isinstance(node, If):
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r = "\t"*level + "if (" + _print_expression(ns, node.cond)[0] + ") begin\n"
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r += _print_node(ns, at, level + 1, node.t, target_filter)
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@ -237,6 +250,8 @@ def _print_node(ns, at, level, node, target_filter=None):
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r += _print_node(ns, at, level + 1, node.f, target_filter)
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r += "\t"*level + "end\n"
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return r
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# Case.
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elif isinstance(node, Case):
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if node.cases:
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r = "\t"*level + "case (" + _print_expression(ns, node.test)[0] + ")\n"
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@ -254,6 +269,8 @@ def _print_node(ns, at, level, node, target_filter=None):
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return r
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else:
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return ""
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# Display.
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elif isinstance(node, Display):
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s = "\"" + node.s + "\""
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for arg in node.args:
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@ -263,12 +280,18 @@ def _print_node(ns, at, level, node, target_filter=None):
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else:
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s += str(arg)
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return "\t"*level + "$display(" + s + ");\n"
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# Finish.
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elif isinstance(node, Finish):
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return "\t"*level + "$finish;\n"
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else:
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raise TypeError("Node of unrecognized type: "+str(type(node)))
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# Print Attribute ----------------------------------------------------------------------------------
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# Unknown.
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else:
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raise TypeError(f"Node of unrecognized type: {str(type(node))}")
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# ------------------------------------------------------------------------------------------------ #
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# ATTRIBUTES #
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# ------------------------------------------------------------------------------------------------ #
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def _print_attribute(attr, attr_translate):
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r = ""
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@ -293,7 +316,9 @@ def _print_attribute(attr, attr_translate):
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r = "(* " + r + " *)"
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return r
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# Print Module -------------------------------------------------------------------------------------
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# ------------------------------------------------------------------------------------------------ #
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# MODULE #
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# ------------------------------------------------------------------------------------------------ #
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def _list_comb_wires(f):
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r = set()
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@ -349,7 +374,9 @@ def _print_module(f, ios, name, ns, attr_translate,
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r += "\n"
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return r
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# Print Combinatorial Logic (Simulation) -----------------------------------------------------------
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# ------------------------------------------------------------------------------------------------ #
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# COMBINATORIAL LOGIC #
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# ------------------------------------------------------------------------------------------------ #
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def _print_combinatorial_logic_sim(f, ns, dummy_signal, blocking_assign):
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r = ""
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@ -403,8 +430,6 @@ def _print_combinatorial_logic_sim(f, ns, dummy_signal, blocking_assign):
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r += "\n"
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return r
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# Print Combinatorial Logic (Synthesis) ------------------------------------------------------------
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def _print_combinatorial_logic_synth(f, ns, blocking_assign):
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r = ""
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if f.comb:
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@ -427,7 +452,9 @@ def _print_combinatorial_logic_synth(f, ns, blocking_assign):
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r += "\n"
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return r
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# Print Synchronous Logic --------------------------------------------------------------------------
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# ------------------------------------------------------------------------------------------------ #
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# SYNCHRONOUS LOGIC #
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# ------------------------------------------------------------------------------------------------ #
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def _print_synchronous_logic(f, ns):
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r = ""
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@ -437,7 +464,9 @@ def _print_synchronous_logic(f, ns):
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r += "end\n\n"
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return r
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# Print Specials -----------------------------------------------------------------------------------
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# ------------------------------------------------------------------------------------------------ #
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# SPECIALS #
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# ------------------------------------------------------------------------------------------------ #
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def _print_specials(overrides, specials, ns, add_data_file, attr_translate):
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r = ""
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@ -456,7 +485,9 @@ def _print_specials(overrides, specials, ns, add_data_file, attr_translate):
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r += pr
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return r
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# Convert FHDL to Verilog --------------------------------------------------------------------------
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# ------------------------------------------------------------------------------------------------ #
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# FHDL --> VERILOG #
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# ------------------------------------------------------------------------------------------------ #
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class DummyAttrTranslate(dict):
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def __getitem__(self, k):
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