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fhdl/verilog: Add larger separators.

This commit is contained in:
Florent Kermarrec 2021-10-15 14:55:46 +02:00
parent 5a2399b037
commit 84e8fd0f9e
1 changed files with 52 additions and 21 deletions
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73
litex/gen/fhdl/verilog.py
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@ -27,7 +27,9 @@ from migen.fhdl.specials import Memory
from litex.gen.fhdl.memory import memory_emit_verilog from litex.gen.fhdl.memory import memory_emit_verilog
from litex.build.tools import generated_banner from litex.build.tools import generated_banner
# Reserved Keywords ------------------------------------------------------------------------------- # ------------------------------------------------------------------------------------------------ #
# RESERVED KEYWORDS #
# ------------------------------------------------------------------------------------------------ #
_ieee_1800_2017_verilog_reserved_keywords = { _ieee_1800_2017_verilog_reserved_keywords = {
"accept_on", "alias", "always", "always_comb", "always_ff", "accept_on", "alias", "always", "always_comb", "always_ff",
@ -82,14 +84,9 @@ _ieee_1800_2017_verilog_reserved_keywords = {
"wor", "xnor", "xor", "wor", "xnor", "xor",
} }
# Print Signal ------------------------------------------------------------------------------------- # ------------------------------------------------------------------------------------------------ #
# EXPRESSIONS #
def _print_signal(ns, s): # ------------------------------------------------------------------------------------------------ #
return "{signed}{vector}{name}".format(
signed = "" if (not s.signed) else "signed ",
vector = "" if ( len(s) <= 1) else f"[{str(len(s)-1) }:0] ",
name = ns.get_name(s)
)
# Print Constant ----------------------------------------------------------------------------------- # Print Constant -----------------------------------------------------------------------------------
@ -100,6 +97,15 @@ def _print_constant(node):
value = abs(node.value), value = abs(node.value),
), node.signed ), node.signed
# Print Signal -------------------------------------------------------------------------------------
def _print_signal(ns, s):
return "{signed}{vector}{name}".format(
signed = "" if (not s.signed) else "signed ",
vector = "" if ( len(s) <= 1) else f"[{str(len(s)-1) }:0] ",
name = ns.get_name(s)
)
# Print Operator ----------------------------------------------------------------------------------- # Print Operator -----------------------------------------------------------------------------------
(UNARY, BINARY, TERNARY) = (1, 2, 3) (UNARY, BINARY, TERNARY) = (1, 2, 3)
@ -209,14 +215,17 @@ def _print_expression(ns, node):
else: else:
raise TypeError(f"Expression of unrecognized type: '{type(node).__name__}'") raise TypeError(f"Expression of unrecognized type: '{type(node).__name__}'")
# ------------------------------------------------------------------------------------------------ #
# Print Node --------------------------------------------------------------------------------------- # NODES #
# ------------------------------------------------------------------------------------------------ #
(_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3) (_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)
def _print_node(ns, at, level, node, target_filter=None): def _print_node(ns, at, level, node, target_filter=None):
if target_filter is not None and target_filter not in list_targets(node): if target_filter is not None and target_filter not in list_targets(node):
return "" return ""
# Assignment.
elif isinstance(node, _Assign): elif isinstance(node, _Assign):
if at == _AT_BLOCKING: if at == _AT_BLOCKING:
assignment = " = " assignment = " = "
@ -227,8 +236,12 @@ def _print_node(ns, at, level, node, target_filter=None):
else: else:
assignment = " <= " assignment = " <= "
return "\t"*level + _print_expression(ns, node.l)[0] + assignment + _print_expression(ns, node.r)[0] + ";\n" return "\t"*level + _print_expression(ns, node.l)[0] + assignment + _print_expression(ns, node.r)[0] + ";\n"
# Iterable.
elif isinstance(node, collections.abc.Iterable): elif isinstance(node, collections.abc.Iterable):
return "".join(_print_node(ns, at, level, n, target_filter) for n in node) return "".join(_print_node(ns, at, level, n, target_filter) for n in node)
# If.
elif isinstance(node, If): elif isinstance(node, If):
r = "\t"*level + "if (" + _print_expression(ns, node.cond)[0] + ") begin\n" r = "\t"*level + "if (" + _print_expression(ns, node.cond)[0] + ") begin\n"
r += _print_node(ns, at, level + 1, node.t, target_filter) r += _print_node(ns, at, level + 1, node.t, target_filter)
@ -237,6 +250,8 @@ def _print_node(ns, at, level, node, target_filter=None):
r += _print_node(ns, at, level + 1, node.f, target_filter) r += _print_node(ns, at, level + 1, node.f, target_filter)
r += "\t"*level + "end\n" r += "\t"*level + "end\n"
return r return r
# Case.
elif isinstance(node, Case): elif isinstance(node, Case):
if node.cases: if node.cases:
r = "\t"*level + "case (" + _print_expression(ns, node.test)[0] + ")\n" r = "\t"*level + "case (" + _print_expression(ns, node.test)[0] + ")\n"
@ -254,6 +269,8 @@ def _print_node(ns, at, level, node, target_filter=None):
return r return r
else: else:
return "" return ""
# Display.
elif isinstance(node, Display): elif isinstance(node, Display):
s = "\"" + node.s + "\"" s = "\"" + node.s + "\""
for arg in node.args: for arg in node.args:
@ -263,12 +280,18 @@ def _print_node(ns, at, level, node, target_filter=None):
else: else:
s += str(arg) s += str(arg)
return "\t"*level + "$display(" + s + ");\n" return "\t"*level + "$display(" + s + ");\n"
# Finish.
elif isinstance(node, Finish): elif isinstance(node, Finish):
return "\t"*level + "$finish;\n" return "\t"*level + "$finish;\n"
else:
raise TypeError("Node of unrecognized type: "+str(type(node)))
# Print Attribute ---------------------------------------------------------------------------------- # Unknown.
else:
raise TypeError(f"Node of unrecognized type: {str(type(node))}")
# ------------------------------------------------------------------------------------------------ #
# ATTRIBUTES #
# ------------------------------------------------------------------------------------------------ #
def _print_attribute(attr, attr_translate): def _print_attribute(attr, attr_translate):
r = "" r = ""
@ -293,7 +316,9 @@ def _print_attribute(attr, attr_translate):
r = "(* " + r + " *)" r = "(* " + r + " *)"
return r return r
# Print Module ------------------------------------------------------------------------------------- # ------------------------------------------------------------------------------------------------ #
# MODULE #
# ------------------------------------------------------------------------------------------------ #
def _list_comb_wires(f): def _list_comb_wires(f):
r = set() r = set()
@ -349,7 +374,9 @@ def _print_module(f, ios, name, ns, attr_translate,
r += "\n" r += "\n"
return r return r
# Print Combinatorial Logic (Simulation) ----------------------------------------------------------- # ------------------------------------------------------------------------------------------------ #
# COMBINATORIAL LOGIC #
# ------------------------------------------------------------------------------------------------ #
def _print_combinatorial_logic_sim(f, ns, dummy_signal, blocking_assign): def _print_combinatorial_logic_sim(f, ns, dummy_signal, blocking_assign):
r = "" r = ""
@ -403,8 +430,6 @@ def _print_combinatorial_logic_sim(f, ns, dummy_signal, blocking_assign):
r += "\n" r += "\n"
return r return r
# Print Combinatorial Logic (Synthesis) ------------------------------------------------------------
def _print_combinatorial_logic_synth(f, ns, blocking_assign): def _print_combinatorial_logic_synth(f, ns, blocking_assign):
r = "" r = ""
if f.comb: if f.comb:
@ -427,7 +452,9 @@ def _print_combinatorial_logic_synth(f, ns, blocking_assign):
r += "\n" r += "\n"
return r return r
# Print Synchronous Logic -------------------------------------------------------------------------- # ------------------------------------------------------------------------------------------------ #
# SYNCHRONOUS LOGIC #
# ------------------------------------------------------------------------------------------------ #
def _print_synchronous_logic(f, ns): def _print_synchronous_logic(f, ns):
r = "" r = ""
@ -437,7 +464,9 @@ def _print_synchronous_logic(f, ns):
r += "end\n\n" r += "end\n\n"
return r return r
# Print Specials ----------------------------------------------------------------------------------- # ------------------------------------------------------------------------------------------------ #
# SPECIALS #
# ------------------------------------------------------------------------------------------------ #
def _print_specials(overrides, specials, ns, add_data_file, attr_translate): def _print_specials(overrides, specials, ns, add_data_file, attr_translate):
r = "" r = ""
@ -456,7 +485,9 @@ def _print_specials(overrides, specials, ns, add_data_file, attr_translate):
r += pr r += pr
return r return r
# Convert FHDL to Verilog -------------------------------------------------------------------------- # ------------------------------------------------------------------------------------------------ #
# FHDL --> VERILOG #
# ------------------------------------------------------------------------------------------------ #
class DummyAttrTranslate(dict): class DummyAttrTranslate(dict):
def __getitem__(self, k): def __getitem__(self, k):