genlib/CRG: fix variable name conflict
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@ -48,12 +48,12 @@ class CRG(Module):
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clk = clk_se
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clk = clk_se
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# Power on Reset (vendor agnostic)
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# Power on Reset (vendor agnostic)
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rst = Signal(reset=1)
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int_rst = Signal(reset=1)
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self.sync.por += rst.eq(rst)
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self.sync.por += int_rst.eq(rst)
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self.comb += [
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self.comb += [
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self.cd_sys.clk.eq(clk),
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self.cd_sys.clk.eq(clk),
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self.cd_por.clk.eq(clk),
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self.cd_por.clk.eq(clk),
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self.cd_sys.rst.eq(rst)
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self.cd_sys.rst.eq(int_rst)
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]
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]
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