cpu/openc906: add debug variant that connects CPU DM to main bus
The OpenC906 CPU core contains a RISC-V debug spec 0.13 compliant DM with APB as its interface. Add a CPU variant "debug" that will connect that APB to the main bus for debugging. Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
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@ -16,6 +16,42 @@ from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
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# Helpers ------------------------------------------------------------------------------------------
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apb_layout = [
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("paddr", 32),
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("pwdata", 32),
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("pwrite", 1),
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("psel", 1),
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("penable", 1),
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("prdata", 32),
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("pready", 1),
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("pslverr", 1),
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]
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# Wishbone <> APB ----------------------------------------------------------------------------------
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class Wishbone2APB(Module):
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def __init__(self, wb, apb):
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assert wb.data_width == 32
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(wb.cyc & wb.stb,
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NextState("ACK"),
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)
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)
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fsm.act("ACK",
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apb.penable.eq(1),
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wb.ack.eq(1),
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NextState("IDLE"),
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)
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self.comb += [
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apb.paddr.eq(Cat(Signal(2), wb.adr)),
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apb.pwrite.eq(wb.we),
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apb.psel.eq(1),
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apb.pwdata.eq(wb.dat_w),
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wb.dat_r.eq(apb.prdata),
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]
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def add_manifest_sources(platform, manifest):
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basedir = os.path.join(os.environ["OPENC906_DIR"], "C906_RTL_FACTORY")
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with open(os.path.join(basedir, manifest), 'r') as f:
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@ -34,7 +70,7 @@ class OpenC906(CPU):
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family = "riscv"
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name = "openc906"
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human_name = "OpenC906"
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variants = ["standard"]
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variants = ["standard", "debug"]
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data_width = 128
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endianness = "little"
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gcc_triple = CPU_GCC_TRIPLE_RISCV64
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@ -64,6 +100,7 @@ class OpenC906(CPU):
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"plic": 0x9000_0000, # Region 1, Strong Order, Non-cacheable, Non-bufferable
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"clint": 0x9400_0000, # Region 1 too
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"ethmac": 0x9800_0000, # Region 1 too
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"riscv_dm": 0x9fff_f000, # Region 1 too
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"csr": 0xa000_0000, # Region 1 too
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}
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@ -150,6 +187,9 @@ class OpenC906(CPU):
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i_pad_biu_rlast = axi_if.r.last,
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)
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if "debug" in variant:
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self.add_debug()
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# Add Verilog sources.
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add_manifest_sources(platform, "gen_rtl/filelists/C906_asic_rtl.fl")
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from litex.build.xilinx import XilinxPlatform
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@ -160,12 +200,40 @@ class OpenC906(CPU):
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# Import a filelist for generic platforms
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add_manifest_sources(platform, "gen_rtl/filelists/generic_fpga.fl")
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def add_debug(self):
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self.debug_bus = wishbone.Interface()
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debug_apb = Record(apb_layout)
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self.submodules += Wishbone2APB(self.debug_bus, debug_apb)
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self.cpu_params.update(
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i_sys_apb_clk = ClockSignal("sys"),
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i_sys_apb_rst_b = ~ResetSignal("sys") & ~self.reset,
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i_tdt_dmi_paddr = debug_apb.paddr,
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i_tdt_dmi_penable = debug_apb.penable,
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i_tdt_dmi_psel = debug_apb.psel,
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i_tdt_dmi_pwdata = debug_apb.pwdata,
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i_tdt_dmi_pwrite = debug_apb.pwrite,
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o_tdt_dmi_prdata = debug_apb.prdata,
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o_tdt_dmi_pready = debug_apb.pready,
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o_tdt_dmi_pslverr = debug_apb.pslverr,
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)
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def add_soc_components(self, soc, soc_region_cls):
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plic = soc_region_cls(origin=soc.mem_map.get("plic"), size=0x400_0000, cached=False)
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clint = soc_region_cls(origin=soc.mem_map.get("clint"), size=0x400_0000, cached=False)
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soc.bus.add_region(name="plic", region=plic)
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soc.bus.add_region(name="clint", region=clint)
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if "debug" in self.variant:
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soc.bus.add_slave("riscv_dm", self.debug_bus, region=
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soc_region_cls(
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origin = soc.mem_map.get("riscv_dm"),
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size = 0x1000,
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cached = False
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)
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)
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def set_reset_address(self, reset_address):
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self.reset_address = reset_address
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self.cpu_params.update(i_pad_cpu_rvba=Signal(40, reset=reset_address))
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