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csr/sram: fix reads on high addresses when word_bits != 0

This commit is contained in:
Kenneth Ryerson 2013-06-03 21:52:21 +02:00 committed by Sebastien Bourdeauducq
parent e5e3492afe
commit 85813b3b58
1 changed files with 2 additions and 2 deletions
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4
migen/bus/csr.py
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@ -107,10 +107,10 @@ class SRAM(Module):
]
if self._page is None:
self.comb += port.adr.eq(self.bus.adr[word_bits:flen(port.adr)])
self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+flen(port.adr)])
else:
pv = self._page.storage
self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:flen(port.adr)-flen(pv)], pv))
self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+flen(port.adr)-flen(pv)], pv))
def get_csrs(self):
if self._page is None: