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Use new bus API

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This commit is contained in:
Sebastien Bourdeauducq 2012-02-15 16:55:13 +01:00
parent 1368b666df
commit 859c9d8849
3 changed files with 42 additions and 39 deletions
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51
milkymist/lm32/__init__.py
View file

@ -3,40 +3,43 @@ from migen.bus import wishbone
class LM32: class LM32:
def __init__(self): def __init__(self):
self.ibus = i = wishbone.Master() self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Master() self.dbus = d = wishbone.Interface()
self.interrupt = Signal(BV(32)) self.interrupt = Signal(BV(32))
self.ext_break = Signal() self.ext_break = Signal()
self._inst = Instance("lm32_top", self._inst = Instance("lm32_top",
[("I_ADR_O", BV(32)), [("I_ADR_O", BV(32)),
("I_DAT_O", i.dat_o), ("I_DAT_O", i.dat_w),
("I_SEL_O", i.sel_o), ("I_SEL_O", i.sel),
("I_CYC_O", i.cyc_o), ("I_CYC_O", i.cyc),
("I_STB_O", i.stb_o), ("I_STB_O", i.stb),
("I_WE_O", i.we_o), ("I_WE_O", i.we),
("I_CTI_O", i.cti_o), ("I_CTI_O", i.cti),
("I_LOCK_O", BV(1)), ("I_LOCK_O", BV(1)),
("I_BTE_O", i.bte_o), ("I_BTE_O", i.bte),
("D_ADR_O", BV(32)), ("D_ADR_O", BV(32)),
("D_DAT_O", d.dat_o), ("D_DAT_O", d.dat_w),
("D_SEL_O", d.sel_o), ("D_SEL_O", d.sel),
("D_CYC_O", d.cyc_o), ("D_CYC_O", d.cyc),
("D_STB_O", d.stb_o), ("D_STB_O", d.stb),
("D_WE_O", d.we_o), ("D_WE_O", d.we),
("D_CTI_O", d.cti_o), ("D_CTI_O", d.cti),
("D_LOCK_O", BV(1)), ("D_LOCK_O", BV(1)),
("D_BTE_O", d.bte_o)], ("D_BTE_O", d.bte)],
[("interrupt", self.interrupt), [("interrupt", self.interrupt),
#("ext_break", self.ext_break), #("ext_break", self.ext_break),
("I_DAT_I", i.dat_i), ("I_DAT_I", i.dat_r),
("I_ACK_I", i.ack_i), ("I_ACK_I", i.ack),
("I_ERR_I", i.err_i), ("I_ERR_I", i.err),
("I_RTY_I", BV(1)), ("I_RTY_I", BV(1)),
("D_DAT_I", d.dat_i), ("D_DAT_I", d.dat_r),
("D_ACK_I", d.ack_i), ("D_ACK_I", d.ack),
("D_ERR_I", d.err_i), ("D_ERR_I", d.err),
("D_RTY_I", BV(1))], ("D_RTY_I", BV(1))],
[], [],
"clk_i", "clk_i",
"rst_i", "rst_i",
"lm32") "lm32")
@ -45,7 +48,7 @@ class LM32:
comb = [ comb = [
self._inst.ins["I_RTY_I"].eq(0), self._inst.ins["I_RTY_I"].eq(0),
self._inst.ins["D_RTY_I"].eq(0), self._inst.ins["D_RTY_I"].eq(0),
self.ibus.adr_o.eq(self._inst.outs["I_ADR_O"][2:]), self.ibus.adr.eq(self._inst.outs["I_ADR_O"][2:]),
self.dbus.adr_o.eq(self._inst.outs["D_ADR_O"][2:]) self.dbus.adr.eq(self._inst.outs["D_ADR_O"][2:])
] ]
return Fragment(comb=comb, instances=[self._inst]) return Fragment(comb=comb, instances=[self._inst])

16
milkymist/norflash/__init__.py
View file

@ -4,22 +4,22 @@ from migen.corelogic import timeline
class NorFlash: class NorFlash:
def __init__(self, adr_width, rd_timing): def __init__(self, adr_width, rd_timing):
self.bus = wishbone.Slave() self.bus = wishbone.Interface()
self.adr = Signal(BV(adr_width-1)) self.adr = Signal(BV(adr_width-1))
self.d = Signal(BV(16)) self.d = Signal(BV(16))
self.oe_n = Signal() self.oe_n = Signal()
self.we_n = Signal() self.we_n = Signal()
self.ce_n = Signal() self.ce_n = Signal()
self.timeline = timeline.Timeline(self.bus.cyc_i & self.bus.stb_i, self.timeline = timeline.Timeline(self.bus.cyc & self.bus.stb,
[(0, [self.adr.eq(Cat(0, self.bus.adr_i[:adr_width-2]))]), [(0, [self.adr.eq(Cat(0, self.bus.adr[:adr_width-2]))]),
(rd_timing, [ (rd_timing, [
self.bus.dat_o[16:].eq(self.d), self.bus.dat_r[16:].eq(self.d),
self.adr.eq(Cat(1, self.bus.adr_i[:adr_width-2]))]), self.adr.eq(Cat(1, self.bus.adr[:adr_width-2]))]),
(2*rd_timing, [ (2*rd_timing, [
self.bus.dat_o[:16].eq(self.d), self.bus.dat_r[:16].eq(self.d),
self.bus.ack_o.eq(1)]), self.bus.ack.eq(1)]),
(2*rd_timing+1, [ (2*rd_timing+1, [
self.bus.ack_o.eq(0)])]) self.bus.ack.eq(0)])])
def get_fragment(self): def get_fragment(self):
comb = [self.oe_n.eq(0), self.we_n.eq(1), comb = [self.oe_n.eq(0), self.we_n.eq(1),

14
milkymist/sram/__init__.py
View file

@ -3,25 +3,25 @@ from migen.bus import wishbone
class SRAM: class SRAM:
def __init__(self, depth): def __init__(self, depth):
self.bus = wishbone.Slave() self.bus = wishbone.Interface()
self.depth = depth self.depth = depth
def get_fragment(self): def get_fragment(self):
# generate write enable signal # generate write enable signal
we = Signal(BV(4)) we = Signal(BV(4))
comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.we_i & self.bus.sel_i[i]) comb = [we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
for i in range(4)] for i in range(4)]
# split address # split address
nbits = bits_for(self.depth-1) nbits = bits_for(self.depth-1)
partial_adr = Signal(BV(nbits)) partial_adr = Signal(BV(nbits))
comb.append(partial_adr.eq(self.bus.adr_i[:nbits])) comb.append(partial_adr.eq(self.bus.adr[:nbits]))
# generate ack # generate ack
sync = [ sync = [
self.bus.ack_o.eq(0), self.bus.ack.eq(0),
If(self.bus.cyc_i & self.bus.stb_i & ~self.bus.ack_o, If(self.bus.cyc & self.bus.stb & ~self.bus.ack,
self.bus.ack_o.eq(1) self.bus.ack.eq(1)
) )
] ]
# memory # memory
port = MemoryPort(partial_adr, self.bus.dat_o, we, self.bus.dat_i, we_granularity=8) port = MemoryPort(partial_adr, self.bus.dat_r, we, self.bus.dat_w, we_granularity=8)
return Fragment(comb, sync, memories=[Memory(32, self.depth, port)]) return Fragment(comb, sync, memories=[Memory(32, self.depth, port)])