cores/cpu/gowin: re-enable write access to csr bus

2022-01-23 16:34:47 +01:00 · 2022-01-23 16:34:47 +01:00 · 85f892227a
parent 0f44723957
commit 85f892227a
1 changed files with 0 additions and 3 deletions
--- a/litex/soc/cores/cpu/gowin_emcu/core.py
+++ b/litex/soc/cores/cpu/gowin_emcu/core.py
@ -169,9 +169,6 @@ class GowinEMCU(CPU):
        self.periph_buses = [self.pbus]
        ahb_targexp0 = ahb.Interface()
        for s, _ in ahb_targexp0.master_signals:
-            # TODO: due to unexpected writes by the CPU bus is currently forced read-only
-            if s == "write":
-                continue
            self.cpu_params[f"o_TARGEXP0H{s.upper()}"] = getattr(ahb_targexp0, s)
        for s, _ in ahb_targexp0.slave_signals:
            self.cpu_params[f"i_TARGEXP0H{s.upper()}"] = getattr(ahb_targexp0, s)