mibuild -> migen.build

README.md

@@ -48,7 +48,7 @@ http://m-labs.hk/gateware.html
 
 ```python
 from migen.fhdl.std import *
-from mibuild.platforms import m1
+from migen.build.platforms import m1
 plat = m1.Platform()
 led = plat.request("user_led")
 m = Module()

doc/conf.py

@@ -90,7 +90,7 @@ exclude_patterns = ['_build']
 pygments_style = 'sphinx'
 
 # A list of ignored prefixes for module index sorting.
-modindex_common_prefix = ['migen.', 'mibuild.']
+modindex_common_prefix = ['migen.']
 
 numpydoc_show_class_members = False
 

mibuild/altera/__init__.py

@@ -1,2 +0,0 @@
-from mibuild.altera.platform import AlteraPlatform
-from mibuild.altera.programmer import USBBlaster

mibuild/lattice/__init__.py

@@ -1,2 +0,0 @@
-from mibuild.lattice.platform import LatticePlatform
-from mibuild.lattice.programmer import LatticeProgrammer

mibuild/sim/__init__.py

@@ -1 +0,0 @@
-from mibuild.sim.platform import SimPlatform

mibuild/xilinx/__init__.py

@@ -1,2 +0,0 @@
-from mibuild.xilinx.platform import XilinxPlatform
-from mibuild.xilinx.programmer import UrJTAG, XC3SProg, FpgaProg, VivadoProgrammer, iMPACT, Adept

migen/build/altera/__init__.py

@@ -0,0 +1,2 @@
+from migen.build.altera.platform import AlteraPlatform
+from migen.build.altera.programmer import USBBlaster

migen/build/altera/platform.py

@@ -1,5 +1,5 @@
-from mibuild.generic_platform import GenericPlatform
-from mibuild.altera import common, quartus
+from migen.build.generic_platform import GenericPlatform
+from migen.build.altera import common, quartus
 
 
 class AlteraPlatform(GenericPlatform):

migen/build/altera/programmer.py

@@ -1,6 +1,6 @@
 import subprocess
 
-from mibuild.generic_programmer import GenericProgrammer
+from migen.build.generic_programmer import GenericProgrammer
 
 
 class USBBlaster(GenericProgrammer):

migen/build/altera/quartus.py

@@ -5,9 +5,9 @@ import os
 import subprocess
 
 from migen.fhdl.structure import _Fragment
-from mibuild.generic_platform import (Pins, IOStandard, Misc)
 
-from mibuild import tools
+from migen.build.generic_platform import Pins, IOStandard, Misc
+from migen.build import tools
 
 
 def _format_constraint(c, signame, fmt_r):
@@ -92,7 +92,7 @@ def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name):
 
 
 def _run_quartus(build_name, quartus_path):
-    build_script_contents = """# Autogenerated by mibuild
+    build_script_contents = """# Autogenerated by Migen
 
 quartus_map --read_settings_files=on --write_settings_files=off {build_name} -c {build_name}
 quartus_fit --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}

migen/build/fpgalink_programmer.py

@@ -1,7 +1,7 @@
 import os
 
-from mibuild.generic_programmer import GenericProgrammer
-from mibuild.xilinx.programmer import _create_xsvf
+from migen.build.generic_programmer import GenericProgrammer
+from migen.build.xilinx.programmer import _create_xsvf
 
 try:
    import fl

migen/build/generic_platform.py

@@ -7,7 +7,7 @@ from migen.genlib.io import CRG
 from migen.fhdl import verilog, edif
 from migen.util.misc import autotype
 
-from mibuild import tools
+from migen.build import tools
 
 
 class ConstraintError(Exception):

migen/build/lattice/__init__.py

@@ -0,0 +1,2 @@
+from migen.build.lattice.platform import LatticePlatform
+from migen.build.lattice.programmer import LatticeProgrammer

migen/build/lattice/diamond.py

@@ -6,10 +6,10 @@ import subprocess
 import shutil
 
 from migen.fhdl.structure import _Fragment
-from mibuild.generic_platform import *
 
-from mibuild import tools
-from mibuild.lattice import common
+from migen.build.generic_platform import *
+from migen.build import tools
+from migen.build.lattice import common
 
 
 def _format_constraint(c):
@@ -60,7 +60,7 @@ def _build_files(device, sources, vincpaths, build_name):
 
 def _run_diamond(build_name, source, ver=None):
     if sys.platform == "win32" or sys.platform == "cygwin":
-        build_script_contents = "REM Autogenerated by mibuild\n"
+        build_script_contents = "REM Autogenerated by Migen\n"
         build_script_contents = "pnmainc " + build_name + ".tcl\n"
         build_script_file = "build_" + build_name + ".bat"
         tools.write_to_file(build_script_file, build_script_contents)

migen/build/lattice/platform.py

@@ -1,5 +1,5 @@
-from mibuild.generic_platform import GenericPlatform
-from mibuild.lattice import common, diamond
+from migen.build.generic_platform import GenericPlatform
+from migen.build.lattice import common, diamond
 
 
 class LatticePlatform(GenericPlatform):

migen/build/lattice/programmer.py

@@ -1,8 +1,9 @@
 import os
 import subprocess
 
-from mibuild.generic_programmer import GenericProgrammer
-from mibuild import tools
+from migen.build.generic_programmer import GenericProgrammer
+from migen.build import tools
+
 
 # XXX Lattice programmer need an .xcf file, will need clean up and support for more parameters
 _xcf_template = """

migen/build/openocd.py

@@ -1,6 +1,6 @@
 import subprocess
 
-from mibuild.generic_programmer import GenericProgrammer
+from migen.build.generic_programmer import GenericProgrammer
 
 
 class OpenOCD(GenericProgrammer):

migen/build/platforms/apf27.py

@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _ios = [
     ("clk0", 0, Pins("N9"), IOStandard("LVCMOS18")),

migen/build/platforms/apf51.py

@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _ios = [
     ("clk3", 0, Pins("N8"), IOStandard("LVCMOS33")),

migen/build/platforms/de0nano.py

@@ -1,9 +1,10 @@
 # This file is Copyright (c) 2013 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
-from mibuild.generic_platform import *
-from mibuild.altera import AlteraPlatform
-from mibuild.altera.programmer import USBBlaster
+from migen.build.generic_platform import *
+from migen.build.altera import AlteraPlatform
+from migen.build.altera.programmer import USBBlaster
+
 
 _io = [
     ("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")),

migen/build/platforms/kc705.py

@@ -1,6 +1,7 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer, iMPACT
-from mibuild.xilinx.ise import XilinxISEToolchain
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer, iMPACT
+from migen.build.xilinx.ise import XilinxISEToolchain
+
 
 _io = [
     ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),

migen/build/platforms/lx9_microboard.py

@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _io = [
         ("user_btn", 0, Pins("V4"), IOStandard("LVCMOS33"),

migen/build/platforms/m1.py

@@ -1,6 +1,7 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
-from mibuild.xilinx.programmer import UrJTAG
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+from migen.build.xilinx.programmer import UrJTAG
+
 
 _io = [
     ("user_led", 0, Pins("B16"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),

migen/build/platforms/mercury.py

@@ -1,9 +1,9 @@
 # This file is Copyright (c) 2015 William D. Jones <thor0505@comcast.net>
 # License: BSD
 
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
-from mibuild.xilinx.programmer import XC3SProg
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+from migen.build.xilinx.programmer import XC3SProg
 
 
 _io = [
@@ -71,7 +71,7 @@ _connectors = [
 ]
 
 # Some default useful extensions- use platform.add_extension() to use, e.g.
-# from mibuild.platforms import mercury
+# from migen.build.platforms import mercury
 # plat = mercury.Platform()
 # plat.add_extension(mercury.gpio_sram)
 

migen/build/platforms/mimasv2.py

@@ -1,5 +1,5 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
 
 
 _io = [

migen/build/platforms/minispartan6.py

@@ -1,9 +1,10 @@
 # This file is Copyright (c) 2015 Matt O'Gorman <mog@rldn.net>
 # License: BSD
 
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
-from mibuild.xilinx.programmer import XC3SProg, FpgaProg
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+from migen.build.xilinx.programmer import XC3SProg, FpgaProg
+
 
 _io = [
     ("user_led", 0, Pins("P11"), IOStandard("LVCMOS33")),

migen/build/platforms/mixxeo.py

@@ -1,6 +1,7 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
-from mibuild.xilinx.programmer import UrJTAG
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+from migen.build.xilinx.programmer import UrJTAG
+
 
 _io = [
     ("user_led", 0, Pins("V5"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),

migen/build/platforms/ml605.py

@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _io = [
     # System clock (Differential 200MHz)

migen/build/platforms/papilio_pro.py

@@ -1,6 +1,7 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
-from mibuild.xilinx.programmer import XC3SProg
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+from migen.build.xilinx.programmer import XC3SProg
+
 
 _io = [
     ("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),

migen/build/platforms/pipistrello.py

@@ -1,6 +1,7 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
-from mibuild.xilinx.programmer import XC3SProg
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+from migen.build.xilinx.programmer import XC3SProg
+
 
 _io = [
     ("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")),  # green at hdmi

migen/build/platforms/rhino.py

@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _io = [
     ("user_led", 0, Pins("Y3")),

migen/build/platforms/roach.py

@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _io = [
     ("epb", 0,

migen/build/platforms/sim.py

@@ -1,5 +1,5 @@
-from mibuild.generic_platform import *
-from mibuild.sim import SimPlatform
+from migen.build.generic_platform import *
+from migen.build.sim import SimPlatform
 
 
 class SimPins(Pins):

migen/build/platforms/usrp_b100.py

@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _io = [
         ("clk64", 0,

migen/build/platforms/versa.py

@@ -1,9 +1,10 @@
 # This file is Copyright (c) 2013 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
-from mibuild.generic_platform import *
-from mibuild.lattice import LatticePlatform
-from mibuild.lattice.programmer import LatticeProgrammer
+from migen.build.generic_platform import *
+from migen.build.lattice import LatticePlatform
+from migen.build.lattice.programmer import LatticeProgrammer
+
 
 _io = [
     ("clk100", 0, Pins("L5"), IOStandard("LVDS25")),

migen/build/platforms/zedboard.py

@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 # Bank 34 and 35 voltage depend on J18 jumper setting
 _io = [

migen/build/platforms/ztex_115d.py

@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _io = [
         ("clk_fx", 0, Pins("L22"), IOStandard("LVCMOS33")),

migen/build/sim/__init__.py

@@ -0,0 +1 @@
+from migen.build.sim.platform import SimPlatform

migen/build/sim/platform.py

@@ -1,5 +1,5 @@
-from mibuild.generic_platform import GenericPlatform
-from mibuild.sim import common, verilator
+from migen.build.generic_platform import GenericPlatform
+from migen.build.sim import common, verilator
 
 
 class SimPlatform(GenericPlatform):

migen/build/sim/verilator.py

@@ -6,10 +6,10 @@ import subprocess
 
 from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
-from mibuild.generic_platform import *
 
-from mibuild import tools
-from mibuild.sim import common
+from migen.build import tools
+from migen.build.generic_platform import *
+from migen.build.sim import common
 
 
 def _build_tb(platform, vns, serial, template):
@@ -90,7 +90,7 @@ def _build_sim(platform, vns, build_name, include_paths, sim_path, serial, verbo
     for path in include_paths:
         include += "-I"+path+" "
 
-    build_script_contents = """# Autogenerated by mibuild
+    build_script_contents = """# Autogenerated by Migen
     rm -rf obj_dir/
 verilator {disable_warnings} -O3 --cc dut.v --exe dut_tb.cpp -LDFLAGS "-lpthread" -trace {include}
 make -j -C obj_dir/ -f Vdut.mk Vdut
@@ -123,7 +123,7 @@ def _run_sim(build_name):
 class SimVerilatorToolchain:
     # XXX fir sim_path
     def build(self, platform, fragment, build_dir="build", build_name="top",
-            sim_path="../migen/mibuild/sim/", serial="console",
+            sim_path="../migen/migen/build/sim/", serial="console",
             run=True, verbose=False):
         tools.mkdir_noerror(build_dir)
         os.chdir(build_dir)

migen/build/xilinx/__init__.py

@@ -0,0 +1,2 @@
+from migen.build.xilinx.platform import XilinxPlatform
+from migen.build.xilinx.programmer import UrJTAG, XC3SProg, FpgaProg, VivadoProgrammer, iMPACT, Adept

migen/build/xilinx/common.py

@@ -7,7 +7,8 @@ from migen.fhdl.specials import SynthesisDirective
 from migen.genlib.cdc import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.io import *
-from mibuild import tools
+
+from migen.build import tools
 
 
 def settings(path, ver=None, sub=None):

migen/build/xilinx/ise.py

@@ -5,9 +5,9 @@ import sys
 from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
 
-from mibuild.generic_platform import *
-from mibuild import tools
-from mibuild.xilinx import common
+from migen.build.generic_platform import *
+from migen.build import tools
+from migen.build.xilinx import common
 
 
 def _format_constraint(c):
@@ -89,12 +89,12 @@ def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
         source_cmd = "call "
         script_ext = ".bat"
         shell = ["cmd", "/c"]
-        build_script_contents = "@echo off\nrem Autogenerated by mibuild\n"
+        build_script_contents = "@echo off\nrem Autogenerated by Migen\n"
     else:
         source_cmd = "source "
         script_ext = ".sh"
         shell = ["bash"]
-        build_script_contents = "# Autogenerated by mibuild\nset -e\n"
+        build_script_contents = "# Autogenerated by Migen\nset -e\n"
     if source:
         settings = common.settings(ise_path, ver, "ISE_DS")
         build_script_contents += source_cmd + settings + "\n"

migen/build/xilinx/platform.py

@@ -1,5 +1,5 @@
-from mibuild.generic_platform import GenericPlatform
-from mibuild.xilinx import common, vivado, ise
+from migen.build.generic_platform import GenericPlatform
+from migen.build.xilinx import common, vivado, ise
 
 
 class XilinxPlatform(GenericPlatform):

migen/build/xilinx/programmer.py

@@ -2,8 +2,8 @@ import os
 import sys
 import subprocess
 
-from mibuild.generic_programmer import GenericProgrammer
-from mibuild.xilinx import common
+from migen.build.generic_programmer import GenericProgrammer
+from migen.build.xilinx import common
 
 
 def _run_urjtag(cmds):

migen/build/xilinx/vivado.py

@@ -7,10 +7,10 @@ import sys
 
 from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
-from mibuild.generic_platform import *
 
-from mibuild import tools
-from mibuild.xilinx import common
+from migen.build.generic_platform import *
+from migen.build import tools
+from migen.build.xilinx import common
 
 
 def _format_constraint(c):
@@ -54,13 +54,13 @@ def _build_xdc(named_sc, named_pc):
 
 def _run_vivado(build_name, vivado_path, source, ver=None):
     if sys.platform == "win32" or sys.platform == "cygwin":
-        build_script_contents = "REM Autogenerated by mibuild\n"
+        build_script_contents = "REM Autogenerated by Migen\n"
         build_script_contents += "vivado -mode batch -source " + build_name + ".tcl\n"
         build_script_file = "build_" + build_name + ".bat"
         tools.write_to_file(build_script_file, build_script_contents)
         r = subprocess.call([build_script_file])
     else:
-        build_script_contents = "# Autogenerated by mibuild\nset -e\n"
+        build_script_contents = "# Autogenerated by Migen\nset -e\n"
         settings = common.settings(vivado_path, ver)
         build_script_contents += "source " + settings + "\n"
         build_script_contents += "vivado -mode batch -source " + build_name + ".tcl\n"