uart2wishbone: add default baudrate
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parent
b94cba2d4b
commit
8719206a3a
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@ -10,9 +10,9 @@ def write_b(uart, data):
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class Uart2Wishbone:
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class Uart2Wishbone:
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WRITE_CMD = 0x01
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WRITE_CMD = 0x01
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READ_CMD = 0x02
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READ_CMD = 0x02
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def __init__(self, port, baudrate, addrmap=None, debug=False):
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def __init__(self, port, baudrate=115200, addrmap=None, debug=False):
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self.port = port
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self.port = port
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self.baudrate = baudrate
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self.baudrate = str(baudrate)
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self.debug = debug
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self.debug = debug
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self.uart = serial.Serial(port, baudrate, timeout=0.25)
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self.uart = serial.Serial(port, baudrate, timeout=0.25)
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self.regs = build_map(addrmap, self.read, self.write)
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self.regs = build_map(addrmap, self.read, self.write)
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@ -161,7 +161,7 @@ class UARTMux(Module):
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class UART2Wishbone(Module, AutoCSR):
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class UART2Wishbone(Module, AutoCSR):
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WRITE_CMD = 0x01
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WRITE_CMD = 0x01
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READ_CMD = 0x02
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READ_CMD = 0x02
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def __init__(self, pads, clk_freq, baud, share_uart=False):
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def __init__(self, pads, clk_freq, baud=115200, share_uart=False):
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# Wishbone interface
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# Wishbone interface
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self.wishbone = wishbone.Interface()
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self.wishbone = wishbone.Interface()
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