sim: update
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@ -5,11 +5,7 @@ from migen.sim.generic import Simulator, PureSimulable, TopLevel
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from migen.sim.icarus import Runner
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from migen.bus.transactions import *
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import sys
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sys.path.append("../")
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from migScope import recorder
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from miscope import recorder
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arm_done = False
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trig_dat = 0
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@ -5,12 +5,8 @@ from migen.sim.generic import Simulator, PureSimulable, TopLevel
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from migen.sim.icarus import Runner
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from migen.bus.transactions import *
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import sys
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sys.path.append("../")
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from migScope import trigger
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from migScope.tools.truthtable import *
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from miscope import trigger
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from miscope.tools.truthtable import *
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def term_prog(off, dat):
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for i in range(4):
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@ -5,12 +5,9 @@ from migen.sim.generic import Simulator, PureSimulable, TopLevel
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from migen.sim.icarus import Runner
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from migen.bus.transactions import *
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import sys
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sys.path.append("../")
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from migScope import trigger, recorder
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from migScope.tools.truthtable import *
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from migScope.tools.vcd import *
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from miscope import trigger, recorder
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from miscope.tools.truthtable import *
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from miscope.tools.vcd import *
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TRIGGER_ADDR = 0x0000
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RECORDER_ADDR = 0x0200
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@ -7,9 +7,7 @@ from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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import sys
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sys.path.append("../")
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import spi2Csr
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import miscope.bridges.spi2csr
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def get_bit(dat, bit):
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return int(dat & (1<<bit) != 0)
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@ -144,7 +142,7 @@ def main():
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bank0 = csrgen.Bank(regs,address=0x0000)
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# Spi2Csr
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spi2csr0 = spi2Csr.Spi2Csr(16,8)
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spi2csr0 = spi2csr.Spi2Csr(16,8)
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# Csr Interconnect
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