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sim: update

This commit is contained in:
Florent Kermarrec 2013-02-26 23:25:10 +01:00
parent ae900c9c16
commit 87336128a3
4 changed files with 8 additions and 21 deletions
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6
sim/tb_RecorderCsr.py
View File

@ -5,11 +5,7 @@ from migen.sim.generic import Simulator, PureSimulable, TopLevel
from migen.sim.icarus import Runner from migen.sim.icarus import Runner
from migen.bus.transactions import * from migen.bus.transactions import *
import sys from miscope import recorder
sys.path.append("../")
from migScope import recorder
arm_done = False arm_done = False
trig_dat = 0 trig_dat = 0

8
sim/tb_TriggerCsr.py
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@ -5,12 +5,8 @@ from migen.sim.generic import Simulator, PureSimulable, TopLevel
from migen.sim.icarus import Runner from migen.sim.icarus import Runner
from migen.bus.transactions import * from migen.bus.transactions import *
import sys from miscope import trigger
sys.path.append("../") from miscope.tools.truthtable import *
from migScope import trigger
from migScope.tools.truthtable import *
def term_prog(off, dat): def term_prog(off, dat):
for i in range(4): for i in range(4):

9
sim/tb_migcope.py → sim/tb_miscope.py
View File

@ -5,12 +5,9 @@ from migen.sim.generic import Simulator, PureSimulable, TopLevel
from migen.sim.icarus import Runner from migen.sim.icarus import Runner
from migen.bus.transactions import * from migen.bus.transactions import *
import sys from miscope import trigger, recorder
sys.path.append("../") from miscope.tools.truthtable import *
from miscope.tools.vcd import *
from migScope import trigger, recorder
from migScope.tools.truthtable import *
from migScope.tools.vcd import *
TRIGGER_ADDR = 0x0000 TRIGGER_ADDR = 0x0000
RECORDER_ADDR = 0x0200 RECORDER_ADDR = 0x0200

6
sim/tb_spi2Csr.py → sim/tb_spi2csr.py
View File

@ -7,9 +7,7 @@ from migen.bus.transactions import *
from migen.bank import description, csrgen from migen.bank import description, csrgen
from migen.bank.description import * from migen.bank.description import *
import sys import miscope.bridges.spi2csr
sys.path.append("../")
import spi2Csr
def get_bit(dat, bit): def get_bit(dat, bit):
return int(dat & (1<<bit) != 0) return int(dat & (1<<bit) != 0)
@ -144,7 +142,7 @@ def main():
bank0 = csrgen.Bank(regs,address=0x0000) bank0 = csrgen.Bank(regs,address=0x0000)
# Spi2Csr # Spi2Csr
spi2csr0 = spi2Csr.Spi2Csr(16,8) spi2csr0 = spi2csr.Spi2Csr(16,8)
# Csr Interconnect # Csr Interconnect