integration/soc/add_sdram: connect to main bus with its data width
Currently we create a 32-bit Wishbone bus, connect LiteDRAM to it and then connect it to the main SoC bus. This prevents us from getting optimized performance from a wider main bus. Make the intermediate bus to have the same width with the main bus. Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
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@ -1581,7 +1581,7 @@ class LiteXSoC(SoC):
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port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2.
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# Create Wishbone Slave.
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wb_sdram = wishbone.Interface()
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wb_sdram = wishbone.Interface(data_width=self.bus.data_width)
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self.bus.add_slave("main_ram", wb_sdram)
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# L2 Cache
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