soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode
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@ -73,12 +73,6 @@ class Zynq7000(CPU):
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io_DDR_VRN = ps7_ddram_pads.vrn,
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io_DDR_VRP = ps7_ddram_pads.vrp,
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# Ethernet
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i_ENET0_MDIO_I = 0,
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# SDIO0
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i_SDIO0_WP = 0,
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# USB0
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i_USB0_VBUS_PWRFAULT = 0,
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@ -86,6 +80,74 @@ class Zynq7000(CPU):
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o_FCLK_CLK0 = ClockSignal("ps7"),
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o_FCLK_RESET0_N = ps7_rst_n
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)
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# Enet0 mdio
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try:
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ps7_enet0_mdio_pads = platform.request("ps7_enet0_mdio")
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self.cpu_params.update(dict(
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o_ENET0_MDIO_MDC = ps7_enet0_mdio_pads.mdc,
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i_ENET0_MDIO_I = ps7_enet0_mdio_pads.i,
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o_ENET0_MDIO_O = ps7_enet0_mdio_pads.o,
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o_ENET0_MDIO_T = ps7_enet0_mdio_pads.t
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))
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except:
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pass
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# Enet0
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try:
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ps7_enet0_pads = platform.request("ps7_enet0")
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self.cpu_params.update(dict(
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o_ENET0_GMII_TX_EN = ps7_enet0_pads.tx_en,
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o_ENET0_GMII_TX_ER = ps7_enet0_pads.tx_er,
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o_ENET0_GMII_TXD = ps7_enet0_pads.txd,
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i_ENET0_GMII_COL = ps7_enet0_pads.col,
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i_ENET0_GMII_CRS = ps7_enet0_pads.crs,
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i_ENET0_GMII_RX_CLK = ps7_enet0_pads.rx_clk,
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i_ENET0_GMII_RX_DV = ps7_enet0_pads.rx_dv,
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i_ENET0_GMII_RX_ER = ps7_enet0_pads.rx_er,
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i_ENET0_GMII_TX_CLK = ps7_enet0_pads.tx_clk,
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i_ENET0_GMII_RXD = ps7_enet0_pads.rxd
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))
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except:
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pass
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# SDIO0
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try:
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ps7_sdio0_pads = platform.request("ps7_sdio0")
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self.cpu_params.update(dict(
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o_SDIO0_CLK = ps7_sdio0_pads.clk,
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i_SDIO0_CLK_FB = ps7_sdio0_pads.clk_fb,
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o_SDIO0_CMD_O = ps7_sdio0_pads.cmd_o,
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i_SDIO0_CMD_I = ps7_sdio0_pads.cmd_i,
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o_SDIO0_CMD_T = ps7_sdio0_pads.cmd_t,
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o_SDIO0_DATA_O = ps7_sdio0_pads.data_o,
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i_SDIO0_DATA_I = ps7_sdio0_pads.data_i,
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o_SDIO0_DATA_T = ps7_sdio0_pads.data_t,
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o_SDIO0_LED = ps7_sdio0_pads.led,
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o_SDIO0_BUSPOW = ps7_sdio0_pads.buspow,
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o_SDIO0_BUSVOLT = ps7_sdio0_pads.busvolt,
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))
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except:
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pass
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# SDIO0_CD
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try:
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ps7_sdio0_cd_pads = platform.request("ps7_sdio0_cd")
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self.cpu_params.update(dict(
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i_SDIO0_CDN = ps7_sdio0_cd_pads.cdn
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))
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except:
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pass
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# SDIO0_WP
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try:
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ps7_sdio0_wp_pads = platform.request("ps7_sdio0_wp")
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self.cpu_params.update(dict(
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i_SDIO0_WP = ps7_sdio0_wp_pads.wp
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))
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except:
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pass
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self.specials += AsyncResetSynchronizer(self.cd_ps7, ~ps7_rst_n)
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def set_ps7_xci(self, ps7_xci):
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