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Merge pull request #623 from Dolu1990/vexriscv_smp 

cpu/vexriscv_smp Add --with-coherent-dma  --without-coherent-dma
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enjoy-digital 2020-08-06 14:31:20 +02:00 committed by GitHub
parent 9a4c5aa1ef 07a8e696ce
commit d5062d1f4f
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 11 additions and 7 deletions
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18
litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -44,13 +44,15 @@ class VexRiscvSMP(CPU):
@staticmethod
def args_fill(parser):
parser.add_argument("--cpu-count", default=1, help="")
parser.add_argument("--dcache-width", default=None, help="L1 data cache bus width")
parser.add_argument("--icache-width", default=None, help="L1 instruction cache bus width")
parser.add_argument("--dcache-size", default=None, help="L1 data cache size in byte per CPU")
parser.add_argument("--dcache-ways", default=None, help="L1 data cache ways per CPU")
parser.add_argument("--icache-size", default=None, help="L1 instruction cache size in byte per CPU")
parser.add_argument("--icache-ways", default=None, help="L1 instruction cache ways per CPU")
parser.add_argument("--cpu-count", default=1, help="")
parser.add_argument("--with-coherent-dma", action='store_true', help="")
parser.add_argument("--without-coherent-dma", action='store_true', help="")
parser.add_argument("--dcache-width", default=None, help="L1 data cache bus width")
parser.add_argument("--icache-width", default=None, help="L1 instruction cache bus width")
parser.add_argument("--dcache-size", default=None, help="L1 data cache size in byte per CPU")
parser.add_argument("--dcache-ways", default=None, help="L1 data cache ways per CPU")
parser.add_argument("--icache-size", default=None, help="L1 instruction cache size in byte per CPU")
parser.add_argument("--icache-ways", default=None, help="L1 instruction cache ways per CPU")
@staticmethod
@ -64,6 +66,8 @@ class VexRiscvSMP(CPU):
VexRiscvSMP.dcache_ways = 2
VexRiscvSMP.icache_ways = 2
VexRiscvSMP.coherent_dma = True
if(args.with_coherent_dma): VexRiscvSMP.coherent_dma = bool(True)
if(args.without_coherent_dma): VexRiscvSMP.coherent_dma = bool(False)
if(args.dcache_width): VexRiscvSMP.dcache_width = int(args.dcache_width)
if(args.icache_width): VexRiscvSMP.icache_width = int(args.icache_width)
if(args.icache_width): VexRiscvSMP.dcache_size = int(args.dcache_size)