Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #598 from sergachev/master 

interconnect/csr_bus: fix paged access warning
This commit is contained in:
enjoy-digital 2020-07-20 19:24:21 +02:00 committed by GitHub
parent 4a18b828bc 8656ea9b67
commit 87d7f6e72e
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/soc/interconnect/csr_bus.py
View File

@ -100,7 +100,7 @@ class SRAM(Module):
page_bits = log2_int((mem.depth*csrw_per_memw + aligned_paging - 1)//aligned_paging, False)
if page_bits:
self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
printf("WARNING: SRAM CSR memory will requires paged access.")
print("WARNING: SRAM CSR memory will require paged access.")
else:
self._page = None
if read_only is None: