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cpu/vexriscv_smp/core: Only raise error with FPU.

This commit is contained in:
Florent Kermarrec 2023-01-16 12:59:14 +01:00
parent a4d5919a2a
commit 88453716dc
1 changed files with 3 additions and 1 deletions
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4
litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -487,8 +487,10 @@ class VexRiscvSMP(CPU):
# When no Direct Memory Bus, do memory accesses through Wishbone Peripheral Bus. # When no Direct Memory Bus, do memory accesses through Wishbone Peripheral Bus.
if len(self.memory_buses) == 0: if len(self.memory_buses) == 0:
if not VexRiscvSMP.wishbone_memory: if VexRiscvSMP.with_fpu and not VexRiscvSMP.wishbone_memory:
raise ValueError("No Direct Memory Bus found, please add --with-wishbone-memory to your build command.") raise ValueError("No Direct Memory Bus found, please add --with-wishbone-memory to your build command.")
else:
VexRiscvSMP.wishbone_memory = True
# Generate cluster name. # Generate cluster name.
VexRiscvSMP.generate_cluster_name() VexRiscvSMP.generate_cluster_name()