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tools/litex_sim: update hybrid etherbone integration

This commit is contained in:
Andrew Dennison 2023-11-13 11:13:19 +11:00
parent fb5512f6d5
commit 885d5b9cb1
1 changed files with 4 additions and 25 deletions
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29
litex/tools/litex_sim.py
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@ -233,29 +233,16 @@ class SimSoC(SoCCore):
else:
raise ValueError("Unknown Ethernet PHY model:", ethernet_phy_model)
# Ethernet and Etherbone -------------------------------------------------------------------
if with_ethernet and with_etherbone:
# Etherbone.
# Etherbone with optional Ethernet ---------------------------------------------------------
if with_etherbone:
self.add_etherbone(
phy = self.ethphy,
ip_address = etherbone_ip_address,
mac_address = etherbone_mac_address,
data_width = 8,
interface = "hybrid",
endianness = self.cpu.endianness
ethernet = with_ethernet,
)
# Software Interface.
self.ethmac = ethmac = self.get_module("ethcore_etherbone").mac
ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant
ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False)
self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region)
# Add IRQs (if enabled).
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# Ethernet ---------------------------------------------------------------------------------
# Ethernet only ----------------------------------------------------------------------------
elif with_ethernet:
# Ethernet MAC
self.ethmac = ethmac = LiteEthMAC(
@ -272,14 +259,6 @@ class SimSoC(SoCCore):
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# Etherbone --------------------------------------------------------------------------------
elif with_etherbone:
self.add_etherbone(
phy = self.ethphy,
ip_address = etherbone_ip_address,
mac_address = etherbone_mac_address
)
# I2C --------------------------------------------------------------------------------------
if with_i2c:
pads = platform.request("i2c", 0)