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Merge pull request #2017 from Dolu1990/vexiiriscv 

Fix VexiiRiscv
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Dolu1990 2024-07-18 11:37:03 +02:00 committed by GitHub
parent 1b9bdbdce4 cbe7413fee
commit 8a08d5ca19
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litex/soc/cores/cpu/vexiiriscv/core.py
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@ -148,7 +148,7 @@ class VexiiRiscv(CPU):
vdir = get_data_mod("cpu", "vexiiriscv").data_location vdir = get_data_mod("cpu", "vexiiriscv").data_location
ndir = os.path.join(vdir, "ext", "VexiiRiscv") ndir = os.path.join(vdir, "ext", "VexiiRiscv")
NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "7b16ef32", args.update_repo) NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "36dad634", args.update_repo)
if not args.cpu_variant: if not args.cpu_variant:
args.cpu_variant = "standard" args.cpu_variant = "standard"