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tools/litex_json2dts_linux: add all soc sys_clk 

Adds clocks for a downstream iclink soc, for example
when builder.add_json() has imported soc clocks.

Node names are as per devicetree fixed-clock.yaml bindings.
This commit is contained in:
Andrew Dennison 2024-05-17 09:46:23 +10:00
parent 23e654db4c
commit 8a0d50b03e
1 changed files with 9 additions and 4 deletions
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13
litex/tools/litex_json2dts_linux.py
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@ -118,13 +118,18 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
# Clocks ------------------------------------------------------------------------------------------
dts += """
sys_clk: pll {{
for c in [c for c in d["constants"].keys() if c.endswith("config_clock_frequency")]:
name = c.removesuffix("config_clock_frequency") + "sys_clk"
dts += """
{name}: clock-{freq} {{
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <{sys_clk_freq}>;
clock-frequency = <{freq}>;
}};
""".format(sys_clk_freq=d["constants"]["config_clock_frequency"])
""".format(
name=name,
freq=d["constants"][c],
)
# CPU ------------------------------------------------------------------------------------------