PureSimulable

This commit is contained in:
Sebastien Bourdeauducq 2012-06-12 17:08:56 +02:00
parent a591510189
commit 8a23451237
5 changed files with 19 additions and 35 deletions

View File

@ -9,7 +9,7 @@ from migen.fhdl.structure import *
from migen.fhdl import verilog
from migen.corelogic.misc import optree
from migen.fhdl import autofragment
from migen.sim.generic import Simulator
from migen.sim.generic import Simulator, PureSimulable
from migen.sim.icarus import Runner
# A synthesizable FIR filter.
@ -38,7 +38,7 @@ class FIR:
# A test bench for our FIR filter.
# Generates a sine wave at the input and records the output.
class TB:
class TB(PureSimulable):
def __init__(self, fir, frequency):
self.fir = fir
self.frequency = frequency
@ -51,9 +51,6 @@ class TB:
s.wr(self.fir.i, int(f*v))
self.inputs.append(v)
self.outputs.append(s.rd(self.fir.o)/f)
def get_fragment(self):
return Fragment(sim=[self.do_simulation])
def main():
# Compute filter coefficients with SciPy.

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@ -1,5 +1,6 @@
from migen.fhdl.structure import *
from migen.flow.actor import *
from migen.sim.generic import PureSimulable
class Token:
def __init__(self, endpoint, value=None):
@ -12,7 +13,7 @@ class Token:
#
# NB: the possibility to push several tokens at once is important to interact
# with actors that only accept a group of tokens when all of them are available.
class SimActor(Actor):
class SimActor(Actor, PureSimulable):
def __init__(self, generator, *endpoint_descriptions, **misc):
self.generator = generator
self.active = set()
@ -66,6 +67,3 @@ class SimActor(Actor):
self._process_transactions(s)
else:
self._next_transactions()
def get_fragment(self):
return Fragment(sim=[self.do_simulation])

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@ -1,7 +1,7 @@
from migen.fhdl.structure import *
from migen.corelogic.misc import optree
from migen.bus.transactions import *
from migen.sim.generic import Proxy
from migen.sim.generic import Proxy, PureSimulable
class FinalizeError(Exception):
pass
@ -170,7 +170,7 @@ class Hub:
]
return ports + Fragment(comb)
class Tap:
class Tap(PureSimulable):
def __init__(self, hub, handler=print):
self.hub = hub
self.handler = handler
@ -209,11 +209,8 @@ class Tap:
transaction = self.tag_to_transaction[hub.tag_call]
transaction.latency = s.cycle_counter - transaction.latency + 1
self.transaction = transaction
def get_fragment(self):
return Fragment(sim=[self.do_simulation])
class Initiator:
class Initiator(PureSimulable):
def __init__(self, port, generator):
self.port = port
self.generator = generator
@ -266,9 +263,6 @@ class Initiator:
next(self._exe)
except StopIteration:
self.done = True
def get_fragment(self):
return Fragment(sim=[self.do_simulation])
class TargetModel:
def __init__(self):
@ -291,7 +285,7 @@ class TargetModel:
self.last_slot += 1
return self.last_slot
class Target:
class Target(PureSimulable):
def __init__(self, hub, model):
self.hub = hub
self.model = model
@ -337,6 +331,3 @@ class Target:
else:
s.wr(self.hub.call, 0)
self._calling_tag = -1
def get_fragment(self):
return Fragment(sim=[self.do_simulation])

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@ -3,7 +3,7 @@ from migen.corelogic import roundrobin
from migen.corelogic.misc import multimux, optree
from migen.bus.simple import *
from migen.bus.transactions import *
from migen.sim.generic import Proxy
from migen.sim.generic import Proxy, PureSimulable
_desc = Description(
(M_TO_S, "adr", 30),
@ -130,7 +130,7 @@ class InterconnectShared:
def get_fragment(self):
return self._arbiter.get_fragment() + self._decoder.get_fragment()
class Tap:
class Tap(PureSimulable):
def __init__(self, bus, handler=print):
self.bus = bus
self.handler = handler
@ -146,11 +146,8 @@ class Tap:
transaction = TRead(s.rd(self.bus.adr),
s.rd(self.bus.dat_r))
self.handler(transaction)
def get_fragment(self):
return Fragment(sim=[self.do_simulation])
class Initiator:
class Initiator(PureSimulable):
def __init__(self, generator):
self.generator = generator
self.bus = Interface()
@ -184,9 +181,6 @@ class Initiator:
else:
s.wr(self.bus.cyc, 0)
s.wr(self.bus.stb, 0)
def get_fragment(self):
return Fragment(sim=[self.do_simulation])
class TargetModel:
def read(self, address):
@ -198,7 +192,7 @@ class TargetModel:
def can_ack(self, bus):
return True
class Target:
class Target(PureSimulable):
def __init__(self, model):
self.bus = Interface()
self.model = model
@ -214,6 +208,3 @@ class Target:
bus.ack = 1
else:
bus.ack = 0
def get_fragment(self):
return Fragment(sim=[self.do_simulation])

View File

@ -179,3 +179,10 @@ class Proxy:
item = getattr(self._obj, name)
assert(isinstance(item, Signal))
self._sim.wr(item, value)
class PureSimulable:
def do_simulation(self, s):
raise NotImplementedError("Need to overload do_simulation")
def get_fragment(self):
return Fragment(sim=[self.do_simulation])