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PureSimulable
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parent
a591510189
commit
8a23451237
5 changed files with 19 additions and 35 deletions
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@ -9,7 +9,7 @@ from migen.fhdl.structure import *
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from migen.fhdl import verilog
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from migen.corelogic.misc import optree
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from migen.fhdl import autofragment
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from migen.sim.generic import Simulator
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from migen.sim.generic import Simulator, PureSimulable
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from migen.sim.icarus import Runner
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# A synthesizable FIR filter.
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@ -38,7 +38,7 @@ class FIR:
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# A test bench for our FIR filter.
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# Generates a sine wave at the input and records the output.
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class TB:
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class TB(PureSimulable):
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def __init__(self, fir, frequency):
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self.fir = fir
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self.frequency = frequency
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@ -51,9 +51,6 @@ class TB:
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s.wr(self.fir.i, int(f*v))
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self.inputs.append(v)
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self.outputs.append(s.rd(self.fir.o)/f)
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def get_fragment(self):
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return Fragment(sim=[self.do_simulation])
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def main():
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# Compute filter coefficients with SciPy.
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@ -1,5 +1,6 @@
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from migen.fhdl.structure import *
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from migen.flow.actor import *
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from migen.sim.generic import PureSimulable
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class Token:
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def __init__(self, endpoint, value=None):
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@ -12,7 +13,7 @@ class Token:
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#
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# NB: the possibility to push several tokens at once is important to interact
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# with actors that only accept a group of tokens when all of them are available.
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class SimActor(Actor):
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class SimActor(Actor, PureSimulable):
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def __init__(self, generator, *endpoint_descriptions, **misc):
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self.generator = generator
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self.active = set()
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@ -66,6 +67,3 @@ class SimActor(Actor):
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self._process_transactions(s)
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else:
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self._next_transactions()
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def get_fragment(self):
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return Fragment(sim=[self.do_simulation])
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@ -1,7 +1,7 @@
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from migen.fhdl.structure import *
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from migen.corelogic.misc import optree
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from migen.bus.transactions import *
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from migen.sim.generic import Proxy
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from migen.sim.generic import Proxy, PureSimulable
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class FinalizeError(Exception):
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pass
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@ -170,7 +170,7 @@ class Hub:
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]
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return ports + Fragment(comb)
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class Tap:
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class Tap(PureSimulable):
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def __init__(self, hub, handler=print):
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self.hub = hub
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self.handler = handler
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@ -209,11 +209,8 @@ class Tap:
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transaction = self.tag_to_transaction[hub.tag_call]
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transaction.latency = s.cycle_counter - transaction.latency + 1
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self.transaction = transaction
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def get_fragment(self):
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return Fragment(sim=[self.do_simulation])
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class Initiator:
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class Initiator(PureSimulable):
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def __init__(self, port, generator):
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self.port = port
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self.generator = generator
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@ -266,9 +263,6 @@ class Initiator:
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next(self._exe)
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except StopIteration:
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self.done = True
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def get_fragment(self):
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return Fragment(sim=[self.do_simulation])
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class TargetModel:
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def __init__(self):
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@ -291,7 +285,7 @@ class TargetModel:
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self.last_slot += 1
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return self.last_slot
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class Target:
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class Target(PureSimulable):
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def __init__(self, hub, model):
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self.hub = hub
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self.model = model
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@ -337,6 +331,3 @@ class Target:
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else:
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s.wr(self.hub.call, 0)
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self._calling_tag = -1
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def get_fragment(self):
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return Fragment(sim=[self.do_simulation])
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@ -3,7 +3,7 @@ from migen.corelogic import roundrobin
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from migen.corelogic.misc import multimux, optree
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from migen.bus.simple import *
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from migen.bus.transactions import *
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from migen.sim.generic import Proxy
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from migen.sim.generic import Proxy, PureSimulable
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_desc = Description(
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(M_TO_S, "adr", 30),
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@ -130,7 +130,7 @@ class InterconnectShared:
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def get_fragment(self):
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return self._arbiter.get_fragment() + self._decoder.get_fragment()
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class Tap:
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class Tap(PureSimulable):
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def __init__(self, bus, handler=print):
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self.bus = bus
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self.handler = handler
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@ -146,11 +146,8 @@ class Tap:
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transaction = TRead(s.rd(self.bus.adr),
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s.rd(self.bus.dat_r))
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self.handler(transaction)
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def get_fragment(self):
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return Fragment(sim=[self.do_simulation])
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class Initiator:
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class Initiator(PureSimulable):
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def __init__(self, generator):
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self.generator = generator
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self.bus = Interface()
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@ -184,9 +181,6 @@ class Initiator:
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else:
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s.wr(self.bus.cyc, 0)
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s.wr(self.bus.stb, 0)
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def get_fragment(self):
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return Fragment(sim=[self.do_simulation])
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class TargetModel:
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def read(self, address):
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@ -198,7 +192,7 @@ class TargetModel:
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def can_ack(self, bus):
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return True
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class Target:
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class Target(PureSimulable):
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def __init__(self, model):
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self.bus = Interface()
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self.model = model
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@ -214,6 +208,3 @@ class Target:
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bus.ack = 1
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else:
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bus.ack = 0
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def get_fragment(self):
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return Fragment(sim=[self.do_simulation])
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@ -179,3 +179,10 @@ class Proxy:
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item = getattr(self._obj, name)
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assert(isinstance(item, Signal))
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self._sim.wr(item, value)
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class PureSimulable:
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def do_simulation(self, s):
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raise NotImplementedError("Need to overload do_simulation")
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def get_fragment(self):
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return Fragment(sim=[self.do_simulation])
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