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boards/platforms: update xilinx programmers.

This commit is contained in:
Florent Kermarrec 2020-05-06 16:16:41 +02:00
parent 3c34039b73
commit 8b9aa16d2e
5 changed files with 5 additions and 5 deletions
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2
litex/boards/platforms/arty.py
View File

@ -259,7 +259,7 @@ class Platform(XilinxPlatform):
def create_programmer(self):
bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
return OpenOCD("openocd_xilinx_xc7.cfg", bscan_spi)
return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex/boards/platforms/genesys2.py
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@ -117,7 +117,7 @@ class Platform(XilinxPlatform):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit")
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex/boards/platforms/kc705.py
View File

@ -549,7 +549,7 @@ set_property CONFIG_VOLTAGE 2.5 [current_design]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit")
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex/boards/platforms/nexys4ddr.py
View File

@ -132,7 +132,7 @@ class Platform(XilinxPlatform):
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a100t.bit")
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a100t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

2
litex/boards/platforms/nexys_video.py
View File

@ -232,7 +232,7 @@ class Platform(XilinxPlatform):
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
def create_programmer(self):
return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit")
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a200t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)