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sim: memory support

This commit is contained in:
Sebastien Bourdeauducq 2015-09-19 23:21:46 +08:00
parent 1861ae9d01
commit 8bbfaa01fc
1 changed files with 6 additions and 3 deletions
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9
migen/sim.py
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@ -5,6 +5,7 @@ from migen.fhdl.structure import (_Operator, _Slice, _ArrayProxy,
_Assign, _Fragment) _Assign, _Fragment)
from migen.fhdl.bitcontainer import flen from migen.fhdl.bitcontainer import flen
from migen.fhdl.tools import list_targets from migen.fhdl.tools import list_targets
from migen.fhdl.simplify import FullMemoryWE, MemoryToArray
__all__ = ["Simulator"] __all__ = ["Simulator"]
@ -114,7 +115,7 @@ class Evaluator:
return self.eval(node.choices[self.eval(node.key, postcommit)], return self.eval(node.choices[self.eval(node.key, postcommit)],
postcommit) postcommit)
else: else:
# TODO: ClockSignal, ResetSignal, Memory # TODO: ClockSignal, ResetSignal
raise NotImplementedError raise NotImplementedError
def assign(self, node, value): def assign(self, node, value):
@ -129,7 +130,7 @@ class Evaluator:
nbits = flen(element) nbits = flen(element)
self.assign(element, value & (2**nbits-1)) self.assign(element, value & (2**nbits-1))
value >>= nbits value >>= nbits
elif isinstance(node, Slice): elif isinstance(node, _Slice):
full_value = self.eval(node, True) full_value = self.eval(node, True)
# clear bits assigned to by the slice # clear bits assigned to by the slice
full_value &= ~((2**node.stop-1) - (2**node.start-1)) full_value &= ~((2**node.stop-1) - (2**node.start-1))
@ -140,7 +141,7 @@ class Evaluator:
elif isinstance(node, _ArrayProxy): elif isinstance(node, _ArrayProxy):
self.assign(node.choices[self.eval(node.key)], value) self.assign(node.choices[self.eval(node.key)], value)
else: else:
# TODO: ClockSignal, ResetSignal, Memory # TODO: ClockSignal, ResetSignal
raise NotImplementedError raise NotImplementedError
def execute(self, statements): def execute(self, statements):
@ -181,6 +182,8 @@ class Simulator:
else: else:
self.generators[k] = [v] self.generators[k] = [v]
FullMemoryWE().transform_fragment(None, self.fragment)
MemoryToArray().transform_fragment(None, self.fragment)
# TODO: insert_resets on sync # TODO: insert_resets on sync
# comb signals return to their reset value if nothing assigns them # comb signals return to their reset value if nothing assigns them
self.fragment.comb[0:0] = [s.eq(s.reset) self.fragment.comb[0:0] = [s.eq(s.reset)