soc/integration: initial adaptation to new SoC class
This commit is contained in:
Florent Kermarrec
parent
6baa07a69b
commit
8bc420679a
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@ -25,6 +25,7 @@ from litex.soc.cores import cpu
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr
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from litex.soc.integration.common import *
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from litex.soc.integration.soc import SoCRegion, SoC
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__all__ = [
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"mem_decoder",
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@ -69,7 +70,7 @@ class SoCController(Module, AutoCSR):
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# SoCCore ------------------------------------------------------------------------------------------
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class SoCCore(Module):
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class SoCCore(SoC):
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# default register/interrupt/memory mappings (can be redefined by user)
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csr_map = {}
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interrupt_map = {}
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@ -106,6 +107,24 @@ class SoCCore(Module):
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self.platform = platform
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self.clk_freq = clk_freq
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SoC.__init__(self,
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bus_standard = "wishbone",
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bus_data_width = 32,
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bus_address_width = 32,
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bus_timeout = wishbone_timeout_cycles,
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bus_reserved_regions = {},
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csr_data_width = csr_data_width,
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csr_address_width = csr_address_width,
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csr_alignment = csr_alignment,
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csr_paging = 0x800,
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csr_reserved_csrs = self.csr_map,
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irq_n_irqs = 32,
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irq_reserved_irqs = {},
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)
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self.mem_regions = self.bus.regions
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# SoC's CSR/Mem/Interrupt mapping (default or user defined + dynamically allocateds)
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self.soc_csr_map = {}
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self.soc_interrupt_map = {}
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@ -115,18 +134,11 @@ class SoCCore(Module):
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# SoC's Config/Constants/Regions
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self.config = {}
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self.constants = {}
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self.mem_regions = {}
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self.csr_regions = {}
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# Wishbone masters/slaves lists
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self._wb_masters = []
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self._wb_slaves = []
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# CSR masters list
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self._csr_masters = []
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self.add_retro_compat(kwargs)
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# Parameters managment ---------------------------------------------------------------------
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if cpu_type == "None":
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cpu_type = None
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@ -142,12 +154,9 @@ class SoCCore(Module):
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self.integrated_sram_size = integrated_sram_size
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self.integrated_main_ram_size = integrated_main_ram_size
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assert csr_data_width in [8, 16, 32]
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self.csr_data_width = csr_data_width
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self.csr_address_width = csr_address_width
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assert csr_alignment in [32, 64]
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self.with_ctrl = with_ctrl
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self.with_uart = with_uart
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@ -158,14 +167,10 @@ class SoCCore(Module):
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# Modules instances ------------------------------------------------------------------------
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# Add user's CSRs (needs to be done before the first dynamic allocation)
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for _name, _id in self.csr_map.items():
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self.add_csr(_name, _id)
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# Add SoCController
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if with_ctrl:
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self.submodules.ctrl = SoCController()
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self.add_csr("ctrl", allow_user_defined=True)
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self.add_csr("ctrl")
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# Add CPU
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self.config["CPU_TYPE"] = str(cpu_type).upper()
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@ -197,12 +202,12 @@ class SoCCore(Module):
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# Add CPU buses as 32-bit Wishbone masters
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for cpu_bus in self.cpu.buses:
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assert cpu_bus.data_width in [32, 64, 128]
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soc_bus = wishbone.Interface(data_width=32)
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soc_bus = wishbone.Interface(data_width=self.bus.data_width)
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self.submodules += wishbone.Converter(cpu_bus, soc_bus)
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self.add_wb_master(soc_bus)
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# Add CPU CSR (dynamic)
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self.add_csr("cpu", allow_user_defined=True)
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self.add_csr("cpu")
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# Add CPU interrupts
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for _name, _id in self.cpu.interrupts.items():
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@ -258,23 +263,23 @@ class SoCCore(Module):
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else:
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self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate)
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self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
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self.add_csr("uart_phy", allow_user_defined=True)
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self.add_csr("uart", allow_user_defined=True)
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self.add_interrupt("uart", allow_user_defined=True)
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self.add_csr("uart_phy")
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self.add_csr("uart")
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self.add_interrupt("uart")
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# Add Identifier
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if ident:
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if ident_version:
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ident = ident + " " + get_version()
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self.submodules.identifier = identifier.Identifier(ident)
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self.add_csr("identifier_mem", allow_user_defined=True)
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self.add_csr("identifier_mem")
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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# Add Timer
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if with_timer:
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self.submodules.timer0 = timer.Timer()
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self.add_csr("timer0", allow_user_defined=True)
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self.add_interrupt("timer0", allow_user_defined=True)
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self.add_csr("timer0")
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self.add_interrupt("timer0")
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# Add Wishbone to CSR bridge
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self.config["CSR_DATA_WIDTH"] = csr_data_width
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@ -293,77 +298,24 @@ class SoCCore(Module):
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# Methods --------------------------------------------------------------------------------------
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def add_interrupt(self, interrupt_name, interrupt_id=None, allow_user_defined=False):
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# Check that interrupt_name is not already used
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if interrupt_name in self.soc_interrupt_map.keys():
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if allow_user_defined:
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return
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else:
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raise ValueError("Interrupt conflict, {} name already used".format(interrupt_name))
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# Check that interrupt_id is in range
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if interrupt_id is not None and interrupt_id >= 32:
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raise ValueError("{} Interrupt ID out of range ({}, max=31)".format(
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interrupt_name, interrupt_id))
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# Interrupt_id not provided: allocate interrupt to the first available id
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if interrupt_id is None:
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for n in range(32):
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if n not in self.soc_interrupt_map.values():
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self.soc_interrupt_map.update({interrupt_name: n})
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return
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raise ValueError("No more space to allocate {} interrupt".format(interrupt_name))
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# Interrupt_id provided: check that interrupt_id is not already used and add interrupt
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else:
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for _name, _id in self.soc_interrupt_map.items():
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if interrupt_id == _id:
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raise ValueError("Interrupt conflict, {} already used by {} interrupt".format(
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interrupt_id, _name))
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self.soc_interrupt_map.update({interrupt_name: interrupt_id})
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self.irq.add(interrupt_name, interrupt_id)
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def add_csr(self, csr_name, csr_id=None, allow_user_defined=False):
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# Check that csr_name is not already used
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if csr_name in self.soc_csr_map.keys():
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if allow_user_defined:
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return
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else:
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raise ValueError("CSR conflict, {} name already used".format(csr_name))
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# Check that csr_id is in range
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if csr_id is not None and csr_id >= 2**self.csr_address_width:
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raise ValueError("{} CSR ID out of range ({}, max=31)".format(
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csr_name, csr_id))
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# csr_id not provided: allocate csr to the first available id
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if csr_id is None:
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for n in range(2**self.csr_address_width):
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if n not in self.soc_csr_map.values():
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self.soc_csr_map.update({csr_name: n})
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return
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raise ValueError("No more space to allocate {} csr".format(csr_name))
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# csr_id provided: check that csr_id is not already used and add csr
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else:
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for _name, _id in self.soc_csr_map.items():
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if csr_id == _id:
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raise ValueError("CSR conflict, {} already used by {} csr".format(
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csr_id, _name))
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self.soc_csr_map.update({csr_name: csr_id})
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self.csr.add(csr_name, csr_id)
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def initialize_rom(self, data):
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self.rom.mem.init = data
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def add_wb_master(self, wbm):
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if self.finalized:
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raise FinalizeError
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self._wb_masters.append(wbm)
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self.bus.add_master(master=wbm)
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def add_wb_slave(self, address_or_address_decoder, interface, size=None):
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if self.finalized:
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raise FinalizeError
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if size is not None:
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address_decoder = mem_decoder(address_or_address_decoder, size)
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else:
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address_decoder = address_or_address_decoder
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self._wb_slaves.append((address_decoder, interface))
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def add_wb_slave(self, address, interface, size=None):
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wb_name = None
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for name, region in self.bus.regions.items():
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if address == region.origin:
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wb_name = name
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break
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self.bus.add_slave(name=wb_name, slave=interface)
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def add_csr_master(self, csrm):
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# CSR masters are not arbitrated, use this with precaution.
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@ -386,107 +338,17 @@ class SoCCore(Module):
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msg += "- 0x{:08x}-0x{:08x}\n".format(region_origin, region_origin + region_length - 1)
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raise ValueError(msg)
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@staticmethod
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def check_regions_overlap(regions):
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i = 0
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while i < len(regions):
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n0 = list(regions.keys())[i]
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r0 = regions[n0]
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for n1 in list(regions.keys())[i+1:]:
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r1 = regions[n1]
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if ("linker" in r0.type) or ("linker" in r1.type):
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continue
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if r0.origin >= (r1.origin + r1.length):
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continue
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if r1.origin >= (r0.origin + r0.length):
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continue
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return (n0, n1)
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i += 1
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return None
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def alloc_mem_region(self, name, length, type):
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# Use type to limit search regions
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search_regions = []
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if "io" in type:
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for _origin, _length in self.soc_io_regions.items():
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search_regions.append(SoCMemRegion(origin=_origin, length=_length, type=type))
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else:
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search_regions.append(SoCMemRegion(origin=0x00000000, length=0x80000000, type=type))
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# Iterate over search_regions and origin to find a candidate region
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for search_region in search_regions:
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origin = search_region.origin
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while (origin + length) < (search_region.origin + search_region.length):
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# Create a candidate mem region.
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candidate_region = SoCMemRegion(origin=origin, length=length, type=type)
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candidate_overlap = False
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# Check candidate does not overlap with allocated mem regions.
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for _, allocated_region in self.mem_regions.items():
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if self.check_regions_overlap({"0": allocated_region, "1": candidate_region}) is not None:
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origin = allocated_region.origin + allocated_region.length
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candidate_overlap = True
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break
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if not candidate_overlap:
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# If no overlap, the candidate is selected.
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#print("{} region allocated at: {:08x}".format(name, candidate_region.origin))
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return candidate_region
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msg = "Not enough addressable memory space to allocate mem region {} of length 0x{:0x}".format(
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name, length)
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raise ValueError(msg)
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def add_mem_region(self, name, length, type="cached"):
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# Check name conflicts.
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if name in self.mem_regions.keys():
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raise ValueError("Memory region conflict, {} name already used".format(name))
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# Round length to next power of 2.
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length = 2**log2_int(length, False)
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# Get mem origin; if not defined in mem_map, allocate a new mem region, else use mem_map
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# mapping and check for type/overlap conflicts.
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origin = self.mem_map.get(name, None)
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if origin is None:
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self.mem_regions[name] = self.alloc_mem_region(name, length, type)
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else:
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# Check type
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if "io" in type:
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self.check_io_region(name,origin, length)
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# Add region
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self.mem_regions[name] = SoCMemRegion(origin, length, type)
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# Check overlap
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overlap = self.check_regions_overlap(self.mem_regions)
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if overlap is not None:
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o0, o1 = overlap[0], overlap[1]
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raise ValueError("Memory region conflict between {} ({}) and {} ({})".format(
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o0, self.mem_regions[o0],
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o1, self.mem_regions[o1],
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))
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# FIXME: add deprecated warning?
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def add_memory_region(self, name, origin, length, type="cached", io_region=False):
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if io_region: # 2019-10-30: io_region retro-compatibility
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deprecated_warning(": io_region replaced by type=\"io\".")
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type = "io"
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assert name in self.mem_map.keys()
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self.add_mem_region(name, length, type)
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def add_memory_region(self, name, origin, length, type="cached"):
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self.bus.add_region(name, SoCRegion(origin=origin, size=length, cached="cached" in type))
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def register_mem(self, name, address, interface, size=0x10000000):
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self.add_wb_slave(address, interface, size)
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self.add_memory_region(name, address, size)
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self.bus.add_slave(name, interface, SoCRegion(origin=address, size=size))
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def register_rom(self, interface, rom_size=0xa000):
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self.add_wb_slave(self.soc_mem_map["rom"], interface, rom_size)
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self.add_memory_region("rom", self.cpu.reset_address, rom_size)
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def check_csr_range(self, name, addr):
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if addr >= 1<<(self.csr_address_width+2):
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raise ValueError("{} CSR out of range, increase csr_address_width".format(name))
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def check_csr_region(self, name, origin):
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for n, r in self.csr_regions.items():
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if n == name or r.origin == origin:
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raise ValueError("CSR region conflict between {} and {}".format(n, name))
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self.bus.add_slave("rom", interface, SoCRegion(origin=self.cpu.reset_address, size=rom_size))
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def add_csr_region(self, name, origin, busword, obj):
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self.check_io_region(name, origin, 0x800)
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self.check_csr_region(name, origin)
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self.csr_regions[name] = SoCCSRRegion(origin, busword, obj)
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def add_constant(self, name, value=None):
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@ -498,12 +360,12 @@ class SoCCore(Module):
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if memory is not None:
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name = name + "_" + memory.name_override
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try:
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return self.soc_csr_map[name]
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return self.csr.csrs[name]
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except KeyError as e:
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msg = "Undefined \"{}\" CSR.\n".format(name)
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msg += "Avalaible CSRs in {} ({}):\n".format(
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self.__class__.__name__, inspect.getfile(self.__class__))
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for k in sorted(self.soc_csr_map.keys()):
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for k in sorted(self.csr.csrs.keys()):
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msg += "- {}\n".format(k)
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raise RuntimeError(msg)
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except ValueError:
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@ -515,18 +377,22 @@ class SoCCore(Module):
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# Finalization ---------------------------------------------------------------------------------
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def do_finalize(self):
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# retro-compat
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for region in self.bus.regions.values():
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region.length = region.size
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region.type = "cached" if region.cached else "io"
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# Verify CPU has required memories
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if not isinstance(self.cpu, cpu.CPUNone):
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for name in ["rom", "sram"]:
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if name not in self.mem_regions.keys():
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if name not in self.bus.regions.keys():
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raise FinalizeError("CPU needs \"{}\" to be defined as memory or linker region".format(name))
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SoC.do_finalize(self)
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# Add the Wishbone Masters/Slaves interconnect
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if len(self._wb_masters):
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self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
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self._wb_slaves, register=True, timeout_cycles=self.wishbone_timeout_cycles)
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if self.with_ctrl and (self.wishbone_timeout_cycles is not None):
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self.comb += self.ctrl.bus_error.eq(self.wishbonecon.timeout.error)
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self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error)
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# Collect and create CSRs
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self.submodules.csrbankarray = csr_bus.CSRBankArray(self,
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@ -543,13 +409,11 @@ class SoCCore(Module):
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# Check and add CSRs regions
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for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
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self.check_csr_range(name, 0x800*mapaddr)
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self.add_csr_region(name, (self.soc_mem_map["csr"] + 0x800*mapaddr),
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self.csr_data_width, csrs)
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# Check and add Memory regions
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for name, memory, mapaddr, mmap in self.csrbankarray.srams:
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self.check_csr_range(name, 0x800*mapaddr)
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self.add_csr_region(name + "_" + memory.name_override,
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(self.soc_mem_map["csr"] + 0x800*mapaddr),
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self.csr_data_width, memory)
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@ -559,8 +423,7 @@ class SoCCore(Module):
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# Add CSRs / Config items to constants
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for name, constant in self.csrbankarray.constants:
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self.add_constant(name.upper() + "_" + constant.name.upper(),
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constant.value.value)
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self.add_constant(name.upper() + "_" + constant.name.upper(), constant.value.value)
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for name, value in sorted(self.config.items(), key=itemgetter(0)):
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self.add_constant("CONFIG_" + name.upper(), value)
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if isinstance(value, str):
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@ -568,7 +431,7 @@ class SoCCore(Module):
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# Connect interrupts
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if hasattr(self.cpu, "interrupt"):
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for _name, _id in sorted(self.soc_interrupt_map.items()):
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for _name, _id in sorted(self.irq.irqs.items()):
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if _name in self.cpu.interrupts.keys():
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continue
|
||||
if hasattr(self, _name):
|
||||
|
|
@ -577,26 +440,6 @@ class SoCCore(Module):
|
|||
self.comb += self.cpu.interrupt[_id].eq(module.ev.irq)
|
||||
self.constants[_name.upper() + "_INTERRUPT"] = _id
|
||||
|
||||
|
||||
# API retro-compatibility layer ----------------------------------------------------------------
|
||||
# Allow user to build the design the old API for ~3 months after the API change is introduced.
|
||||
# Adds warning and artificical delay to encourage user to update.
|
||||
|
||||
def add_retro_compat(self, kwargs):
|
||||
# 2019-10-09 : deprecate shadow_base, introduce io_regions
|
||||
if "shadow_base" in kwargs.keys():
|
||||
deprecated_warning(": shadow_base replaced by IO regions.")
|
||||
self.retro_compat_shadow_base = kwargs.get("shadow_base", 0x80000000)
|
||||
self.config["SHADOW_BASE"] = self.retro_compat_shadow_base
|
||||
|
||||
def __getattr__(self, name):
|
||||
# 2019-10-09: deprecate shadow_base, introduce io_regions
|
||||
if name == "shadow_base":
|
||||
deprecated_warning(": shadow_base replaced by IO regions.")
|
||||
return self.retro_compat_shadow_base
|
||||
else:
|
||||
return Module.__getattr__(self, name)
|
||||
|
||||
# SoCCore arguments --------------------------------------------------------------------------------
|
||||
|
||||
def soc_core_args(parser):
|
||||
|
|
|
|||
Loading…
Reference in New Issue