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soc/interconnect/stream: fix missing param

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Florent Kermarrec 2016-03-16 16:21:32 +01:00
parent cb47373383
commit 8c272c1f6f
1 changed files with 3 additions and 0 deletions
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3
litex/soc/interconnect/stream.py
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@ -70,6 +70,7 @@ class _FIFOWrapper(Module):
description = self.sink.description description = self.sink.description
fifo_layout = [("payload", description.payload_layout), fifo_layout = [("payload", description.payload_layout),
("param", description.param_layout),
("eop", 1)] ("eop", 1)]
self.submodules.fifo = fifo_class(layout_len(fifo_layout), depth) self.submodules.fifo = fifo_class(layout_len(fifo_layout), depth)
@ -85,10 +86,12 @@ class _FIFOWrapper(Module):
self.fifo.we.eq(self.sink.stb), self.fifo.we.eq(self.sink.stb),
fifo_in.eop.eq(self.sink.eop), fifo_in.eop.eq(self.sink.eop),
fifo_in.payload.eq(self.sink.payload), fifo_in.payload.eq(self.sink.payload),
fifo_in.param.eq(self.sink.param),
self.source.stb.eq(self.fifo.readable), self.source.stb.eq(self.fifo.readable),
self.source.eop.eq(fifo_out.eop), self.source.eop.eq(fifo_out.eop),
self.source.payload.eq(fifo_out.payload), self.source.payload.eq(fifo_out.payload),
self.source.param.eq(fifo_out.param),
self.fifo.re.eq(self.source.ack) self.fifo.re.eq(self.source.ack)
] ]