Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets: add fixed sdcard clock on boards with SDCard support.

This commit is contained in:
Florent Kermarrec 2020-06-25 11:13:24 +02:00
parent c466900322
commit 8c572d2b3e
3 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/boards/targets/nexys4ddr.py
View File

@ -30,6 +30,7 @@ class _CRG(Module):
self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain() self.clock_domains.cd_eth = ClockDomain()
self.clock_domains.cd_sdcard = ClockDomain()
# # # # # #
@ -41,6 +42,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90) pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6) pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_eth, 50e6) pll.create_clkout(self.cd_eth, 50e6)
pll.create_clkout(self.cd_sdcard, 10e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)

2
litex/boards/targets/nexys_video.py
View File

@ -30,6 +30,7 @@ class _CRG(Module):
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_clk100 = ClockDomain() self.clock_domains.cd_clk100 = ClockDomain()
self.clock_domains.cd_sdcard = ClockDomain()
# # # # # #
@ -41,6 +42,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6) pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_clk100, 100e6) pll.create_clkout(self.cd_clk100, 100e6)
pll.create_clkout(self.cd_sdcard, 10e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)

8
litex/boards/targets/ulx3s.py
View File

@ -32,7 +32,7 @@ class _CRG(Module):
def __init__(self, platform, sys_clk_freq, with_usb_pll=False): def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
self.clock_domains.cd_clk10 = ClockDomain() # FIXME: for initial LiteSDCard tests. self.clock_domains.cd_sdcard = ClockDomain()
# # # # # #
@ -46,9 +46,9 @@ class _CRG(Module):
pll.register_clkin(clk25, 25e6) pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk10, 10e6) pll.create_clkout(self.cd_sdcard, 10e6)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
self.specials += AsyncResetSynchronizer(self.cd_clk10, ~pll.locked | rst) self.specials += AsyncResetSynchronizer(self.cd_sdcard, ~pll.locked | rst)
# USB PLL # USB PLL
if with_usb_pll: if with_usb_pll: