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Merge pull request from developandplay/patch-3

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Fix base_address for LiteDRAMWishbone2Native
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enjoy-digital 2021-06-09 08:58:28 +02:00 committed by GitHub
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litex/soc/integration/soc.py
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@ -1326,7 +1326,7 @@ class LiteXSoC(SoC):
self.submodules += LiteDRAMWishbone2Native( self.submodules += LiteDRAMWishbone2Native(
wishbone = litedram_wb, wishbone = litedram_wb,
port = port, port = port,
base_address = origin) base_address = self.bus.regions["main_ram"].origin)
self.submodules += wishbone.Converter(mem_wb, litedram_wb) self.submodules += wishbone.Converter(mem_wb, litedram_wb)
# Check if bus is a Native bus and connect it. # Check if bus is a Native bus and connect it.
if isinstance(mem_bus, LiteDRAMNativePort): if isinstance(mem_bus, LiteDRAMNativePort):