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crg: use new platform.request

This commit is contained in:
Sebastien Bourdeauducq 2013-03-26 23:08:35 +01:00
parent 38e92eb92b
commit 8cf7c96a53
2 changed files with 5 additions and 7 deletions
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7
mibuild/crg.py
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@ -4,9 +4,8 @@ from migen.fhdl.module import Module
class SimpleCRG(Module): class SimpleCRG(Module):
def __init__(self, platform, clk_name, rst_name, rst_invert=False): def __init__(self, platform, clk_name, rst_name, rst_invert=False):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
platform.request(clk_name, None, self.cd_sys.clk) self.comb += self.cd_sys.clk.eq(platform.request(clk_name))
if rst_invert: if rst_invert:
rst_n = platform.request(rst_name) self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
self.comb += self.cd_sys.rst.eq(~rst_n)
else: else:
platform.request(rst_name, None, self.cd_sys.rst) self.comb += self.cd_sys.rst.eq(platform.request(rst_name))

5
mibuild/xilinx_ise.py
View File

@ -24,10 +24,9 @@ class CRG_DS(Module):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self._clk = platform.request(clk_name) self._clk = platform.request(clk_name)
if rst_invert: if rst_invert:
rst_n = platform.request(rst_name) self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
self.comb += self.cd_sys.rst.eq(~rst_n)
else: else:
platform.request(rst_name, None, self.cd_sys.rst) self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
_add_period_constraint(platform, self._clk.p, period) _add_period_constraint(platform, self._clk.p, period)
self.specials += Instance("IBUFGDS", self.specials += Instance("IBUFGDS",
Instance.Input("I", self._clk.p), Instance.Input("I", self._clk.p),