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CHANGES: Update.

This commit is contained in:
Florent Kermarrec 2023-12-08 12:11:37 +01:00
parent 1e5df2dedf
commit 8d6120c476
1 changed files with 2 additions and 0 deletions
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@ -5,6 +5,7 @@
- liteeth/arp : Fixed response on table update. - liteeth/arp : Fixed response on table update.
- litesata/us(p)sataphy : Fixed data_width=32 case. - litesata/us(p)sataphy : Fixed data_width=32 case.
- clock/lattice_ecp5 : Fixed phase calculation. - clock/lattice_ecp5 : Fixed phase calculation.
- interconnect/axi : Fixed AXILite2CSR read access (1 CSR cycle instead of 2).
[> Added [> Added
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@ -32,6 +33,7 @@
- soc/cores/clock : Added proper clock feedback support on Efinix TRIONPLL. - soc/cores/clock : Added proper clock feedback support on Efinix TRIONPLL.
- liteiclink/phy : Added Efinix support/examples on Trion/Titanium. - liteiclink/phy : Added Efinix support/examples on Trion/Titanium.
- liteiclink/serwb : Reused Etherbone from LiteEth to avoid code duplication. - liteiclink/serwb : Reused Etherbone from LiteEth to avoid code duplication.
- interconnect : Added 64-bit support to Wishbone/AXI-Lite/AXI.
[> Changed [> Changed
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