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boards/targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support.

This commit is contained in:
Florent Kermarrec 2020-03-24 20:04:18 +01:00
parent 3eb08c7dd8
commit 8d999081e3
3 changed files with 12 additions and 19 deletions
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9
litex/boards/targets/de0nano.py
View File

@ -22,7 +22,7 @@ from litedram.phy import GENSDRPHY
class _CRG(Module): class _CRG(Module):
def __init__(self, platform): def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# # # # # #
@ -43,7 +43,7 @@ class _CRG(Module):
p_CLK1_DIVIDE_BY = 1, p_CLK1_DIVIDE_BY = 1,
p_CLK1_DUTY_CYCLE = 50, p_CLK1_DUTY_CYCLE = 50,
p_CLK1_MULTIPLY_BY = 1, p_CLK1_MULTIPLY_BY = 1,
p_CLK1_PHASE_SHIFT = "-10000", p_CLK1_PHASE_SHIFT = "5000", # 90°
p_COMPENSATE_CLOCK = "CLK0", p_COMPENSATE_CLOCK = "CLK0",
p_INCLK0_INPUT_FREQUENCY = 20000, p_INCLK0_INPUT_FREQUENCY = 20000,
p_OPERATION_MODE = "NORMAL", p_OPERATION_MODE = "NORMAL",
@ -61,10 +61,7 @@ class _CRG(Module):
self.cd_sys.clk.eq(pll_clk_out[0]), self.cd_sys.clk.eq(pll_clk_out[0]),
self.cd_sys_ps.clk.eq(pll_clk_out[1]), self.cd_sys_ps.clk.eq(pll_clk_out[1]),
] ]
self.specials += [ self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_locked)
AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked)
]
# SDRAM clock # SDRAM clock
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)

16
litex/boards/targets/minispartan6.py
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@ -9,6 +9,7 @@ import argparse
from fractions import Fraction from fractions import Fraction
from migen import * from migen import *
from migen.genlib.io import DDROutput
from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import minispartan6 from litex.boards.platforms import minispartan6
@ -26,27 +27,22 @@ from litedram.phy import GENSDRPHY
class _CRG(Module): class _CRG(Module):
def __init__(self, platform, clk_freq): def __init__(self, platform, clk_freq):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# # # # # #
self.submodules.pll = pll = S6PLL(speedgrade=-1) self.submodules.pll = pll = S6PLL(speedgrade=-1)
pll.register_clkin(platform.request("clk32"), 32e6) pll.register_clkin(platform.request("clk32"), 32e6)
pll.create_clkout(self.cd_sys, clk_freq) pll.create_clkout(self.cd_sys, clk_freq)
pll.create_clkout(self.cd_sys_ps, clk_freq, phase=270) pll.create_clkout(self.cd_sys_ps, clk_freq, phase=90)
self.specials += Instance("ODDR2", # SDRAM clock
p_DDR_ALIGNMENT="NONE", self.specials += DDROutput(0, 1, platform.request("sdram_clock"), ClockSignal("sys_ps"))
p_INIT=0, p_SRTYPE="SYNC",
i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
o_Q=platform.request("sdram_clock"))
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(80e6), **kwargs): def __init__(self, sys_clk_freq=int(80e6), **kwargs):
assert sys_clk_freq == int(80e6)
platform = minispartan6.Platform() platform = minispartan6.Platform()
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
@ -57,7 +53,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM -------------------------------------------------------------------------------- # SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cmd_latency=2)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = AS4C16M16(sys_clk_freq, "1:1"), module = AS4C16M16(sys_clk_freq, "1:1"),

6
litex/boards/targets/ulx3s.py
View File

@ -40,8 +40,8 @@ class _CRG(Module):
self.submodules.pll = pll = ECP5PLL() self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(rst) self.comb += pll.reset.eq(rst)
pll.register_clkin(clk25, 25e6) pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11) pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
# SDRAM clock # SDRAM clock
@ -66,7 +66,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM -------------------------------------------------------------------------------- # SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, "1:1"), module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, "1:1"),