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Merge pull request #1347 from enjoy-digital/ci-cpus 

test/test_cpu: Re-enable cv32e40p/marocchino.
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enjoy-digital 2022-06-29 11:52:27 +02:00 committed by GitHub
parent 7388684232 9c3663f3d2
commit 8eae77a310
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1 changed files with 3 additions and 3 deletions
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test/test_cpu.py
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@ -36,13 +36,12 @@ class TestCPU(unittest.TestCase):
def test_cpu(self): def test_cpu(self):
tested_cpus = [ tested_cpus = [
#"cv32e40p", # (riscv / softcore) "cv32e40p", # (riscv / softcore)
"femtorv", # (riscv / softcore) "femtorv", # (riscv / softcore)
"firev", # (riscv / softcore) "firev", # (riscv / softcore)
"ibex", # (riscv / softcore) "ibex", # (riscv / softcore)
#"marocchino", # (or1k / softcore) "marocchino", # (or1k / softcore)
"naxriscv", # (riscv / softcore) "naxriscv", # (riscv / softcore)
#"rocket", # (riscv / softcore)
"serv", # (riscv / softcore) "serv", # (riscv / softcore)
"vexriscv", # (riscv / softcore) "vexriscv", # (riscv / softcore)
"vexriscv_smp", # (riscv / softcore) "vexriscv_smp", # (riscv / softcore)
@ -62,6 +61,7 @@ class TestCPU(unittest.TestCase):
"mor1kx", # (or1k / softcore) -> Verilator compilation issue. "mor1kx", # (or1k / softcore) -> Verilator compilation issue.
"neorv32", # (riscv / softcore) -> Requires VHDL->Verilog (GHDL + Yosys). "neorv32", # (riscv / softcore) -> Requires VHDL->Verilog (GHDL + Yosys).
"picorv32", # (riscv / softcore) -> Verilator compilation issue. "picorv32", # (riscv / softcore) -> Verilator compilation issue.
"rocket", # (riscv / softcore) -> Not enough RAM in CI.
"zynq7000", # (arm / hardcore) -> Hardcore. "zynq7000", # (arm / hardcore) -> Hardcore.
"zynqmp", # (aarch64 / hardcore) -> Hardcore. "zynqmp", # (aarch64 / hardcore) -> Hardcore.
] ]