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soc/cores/clock/colognechip: REF_CLK/OUT_CLK: int -> str

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Gwenhael Goavec-Merou 2024-02-28 16:11:27 +01:00
parent cd8ad3714d
commit 8eb5e7b6c1
1 changed files with 2 additions and 2 deletions
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4
litex/soc/cores/clock/colognechip.py
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@ -131,8 +131,8 @@ class GateMatePLL(LiteXModule):
freqOutMHz = clkout_freq/1e6
self.specials += Instance("CC_PLL",
p_REF_CLK = freqInMHz, # reference input in MHz
p_OUT_CLK = freqOutMHz, # pll output frequency in MHz
p_REF_CLK = str(freqInMHz), # reference input in MHz
p_OUT_CLK = str(freqOutMHz), # pll output frequency in MHz
p_LOW_JITTER = self._low_jitter, # 0: disable, 1: enable low jitter mode
p_PERF_MD = self._perf_mode, # FPGA operation mode for VDD_PLL
p_LOCK_REQ = self._lock_req, # Lock status required before PLL output enable