simplify UART2Wishbone and add timeout
This commit is contained in:
Florent Kermarrec
parent
54597f1bfc
commit
8f14f67ea6
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@ -7,6 +7,29 @@ from migen.bus import wishbone
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from misoclib.uart import UARTRX, UARTTX
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@DecorateModule(InsertReset)
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@DecorateModule(InsertCE)
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class Counter(Module):
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def __init__(self, signal=None, **kwargs):
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if signal is None:
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self.value = Signal(**kwargs)
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else:
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self.value = signal
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self.width = flen(self.value)
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self.sync += self.value.eq(self.value+1)
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@DecorateModule(InsertReset)
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@DecorateModule(InsertCE)
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class Timeout(Module):
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def __init__(self, length):
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self.reached = Signal()
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###
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value = Signal(max=length)
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self.sync += value.eq(value+1)
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self.comb += [
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self.reached.eq(value == length)
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]
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class UART(Module, AutoCSR):
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def __init__(self, pads, clk_freq, baud=115200):
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self._tuning_word = CSRStorage(32, reset=int((baud/clk_freq)*2**32))
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@ -17,19 +40,6 @@ class UART(Module, AutoCSR):
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self.rx = UARTRX(pads, tuning_word)
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self.tx = UARTTX(pads, tuning_word)
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class Counter(Module):
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def __init__(self, width):
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self.value = Signal(width)
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self.clr = Signal()
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self.inc = Signal()
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self.sync += [
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If(self.clr,
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self.value.eq(0)
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).Elif(self.inc,
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self.value.eq(self.value+1)
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)
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]
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class UARTPads:
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def __init__(self):
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self.rx = Signal()
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@ -64,16 +74,15 @@ class UARTMux(Module):
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)
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class UART2Wishbone(Module, AutoCSR):
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WRITE_CMD = 0x01
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READ_CMD = 0x02
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cmds = {
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"write" : 0x01,
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"read" : 0x02
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}
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def __init__(self, pads, clk_freq, baud=115200, share_uart=False):
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# Wishbone interface
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self.wishbone = wishbone.Interface()
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if share_uart:
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self._sel = CSRStorage()
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###
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###
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if share_uart:
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self.uart_mux = UARTMux(pads)
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self.uart = UART(self.uart_mux.bridge_pads, clk_freq, baud)
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@ -84,118 +93,123 @@ class UART2Wishbone(Module, AutoCSR):
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uart = self.uart
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fsm = FSM()
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self.submodules += fsm
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self.byte_counter = Counter(bits_sign=3)
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self.word_counter = Counter(bits_sign=8)
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word_cnt = Counter(3)
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burst_cnt = Counter(8)
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self.submodules += word_cnt, burst_cnt
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cmd = Signal(8)
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cmd_ce = Signal()
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length = Signal(8)
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length_ce = Signal()
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address = Signal(32)
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address_ce = Signal()
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data = Signal(32)
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rx_data_ce = Signal()
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tx_data_ce = Signal()
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self.sync += [
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If(cmd_ce, cmd.eq(uart.rx.source.d)),
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If(length_ce, length.eq(uart.rx.source.d)),
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If(address_ce, address.eq(Cat(uart.rx.source.d, address[0:24]))),
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If(rx_data_ce,
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data.eq(Cat(uart.rx.source.d, data[0:24]))
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).Elif(tx_data_ce,
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data.eq(self.wishbone.dat_r)
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)
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]
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###
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cmd = Signal(8)
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fsm.act("WAIT_CMD",
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self.fsm = fsm = InsertReset(FSM(reset_state="IDLE"))
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self.timeout = Timeout(clk_freq//10)
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self.comb += [
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self.timeout.ce.eq(1),
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self.fsm.reset.eq(self.timeout.reached)
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]
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fsm.act("IDLE",
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self.timeout.reset.eq(1),
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If(uart.rx.source.stb,
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If( (uart.rx.source.d == self.WRITE_CMD) |
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(uart.rx.source.d == self.READ_CMD),
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NextState("RECEIVE_BURST_LENGTH")
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cmd_ce.eq(1),
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If( (uart.rx.source.d == self.cmds["write"]) |
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(uart.rx.source.d == self.cmds["read"]),
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NextState("RECEIVE_LENGTH")
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),
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word_cnt.clr.eq(1),
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burst_cnt.clr.eq(1)
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self.byte_counter.reset.eq(1),
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self.word_counter.reset.eq(1)
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)
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)
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self.sync += If(fsm.ongoing("WAIT_CMD") & uart.rx.source.stb, cmd.eq(uart.rx.source.d))
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####
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burst_length = Signal(8)
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fsm.act("RECEIVE_BURST_LENGTH",
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word_cnt.inc.eq(uart.rx.source.stb),
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If(word_cnt.value == 1,
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word_cnt.clr.eq(1),
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fsm.act("RECEIVE_LENGTH",
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If(uart.rx.source.stb,
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length_ce.eq(1),
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NextState("RECEIVE_ADDRESS")
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)
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)
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self.sync += \
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If(fsm.ongoing("RECEIVE_BURST_LENGTH") & uart.rx.source.stb, burst_length.eq(uart.rx.source.d))
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####
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address = Signal(32)
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fsm.act("RECEIVE_ADDRESS",
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word_cnt.inc.eq(uart.rx.source.stb),
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If(word_cnt.value == 4,
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word_cnt.clr.eq(1),
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If(cmd == self.WRITE_CMD,
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NextState("RECEIVE_DATA")
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).Elif(cmd == self.READ_CMD,
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NextState("READ_DATA")
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If(uart.rx.source.stb,
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address_ce.eq(1),
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self.byte_counter.ce.eq(1),
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If(self.byte_counter.value == 3,
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If(cmd == self.cmds["write"],
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NextState("RECEIVE_DATA")
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).Elif(cmd == self.cmds["read"],
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NextState("READ_DATA")
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),
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self.byte_counter.reset.eq(1),
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)
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)
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)
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self.sync += \
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If(fsm.ongoing("RECEIVE_ADDRESS") & uart.rx.source.stb,
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address.eq(Cat(uart.rx.source.d, address[0:24]))
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)
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###
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data = Signal(32)
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###
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fsm.act("RECEIVE_DATA",
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word_cnt.inc.eq(uart.rx.source.stb),
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If(word_cnt.value == 4,
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word_cnt.clr.eq(1),
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NextState("WRITE_DATA")
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If(uart.rx.source.stb,
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rx_data_ce.eq(1),
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self.byte_counter.ce.eq(1),
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If(self.byte_counter.value == 3,
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NextState("WRITE_DATA"),
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self.byte_counter.reset.eq(1)
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)
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)
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)
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fsm.act("WRITE_DATA",
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self.wishbone.adr.eq(address + burst_cnt.value),
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self.comb += [
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self.wishbone.adr.eq(address + self.word_counter.value),
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self.wishbone.dat_w.eq(data),
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self.wishbone.sel.eq(2**flen(self.wishbone.sel)-1),
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self.wishbone.sel.eq(2**flen(self.wishbone.sel)-1)
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]
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fsm.act("WRITE_DATA",
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(1),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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burst_cnt.inc.eq(1),
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If(burst_cnt.value == (burst_length-1),
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NextState("WAIT_CMD")
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self.word_counter.ce.eq(1),
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If(self.word_counter.value == (length-1),
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NextState("IDLE")
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).Else(
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word_cnt.clr.eq(1),
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NextState("RECEIVE_DATA")
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)
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)
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)
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###
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fsm.act("READ_DATA",
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self.wishbone.adr.eq(address + burst_cnt.value),
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self.wishbone.sel.eq(2**flen(self.wishbone.sel)-1),
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(0),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.stb & self.wishbone.ack,
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word_cnt.clr.eq(1),
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If(self.wishbone.ack,
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tx_data_ce.eq(1),
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NextState("SEND_DATA")
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)
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)
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self.comb += \
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chooser(data, self.byte_counter.value, uart.tx.sink.d, n=4, reverse=True)
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fsm.act("SEND_DATA",
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word_cnt.inc.eq(uart.tx.sink.ack),
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If(word_cnt.value == 4,
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burst_cnt.inc.eq(1),
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If(burst_cnt.value == (burst_length-1),
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NextState("WAIT_CMD")
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).Else(
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NextState("READ_DATA")
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)
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),
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uart.tx.sink.stb.eq(1),
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chooser(data, word_cnt.value, uart.tx.sink.d, n=4, reverse=True)
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)
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###
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self.sync += \
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If(fsm.ongoing("RECEIVE_DATA") & uart.rx.source.stb,
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data.eq(Cat(uart.rx.source.d, data[0:24]))
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).Elif(fsm.ongoing("READ_DATA") & self.wishbone.stb & self.wishbone.ack,
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data.eq(self.wishbone.dat_r)
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If(uart.tx.sink.ack,
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self.byte_counter.ce.eq(1),
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If(self.byte_counter.value == 3,
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self.word_counter.ce.eq(1),
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If(self.word_counter.value == (length-1),
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NextState("IDLE")
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).Else(
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NextState("READ_DATA"),
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self.byte_counter.reset.eq(1)
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)
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)
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)
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)
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