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soc/cores/hyperbus: Fix build with SDRTristate (to prepare tests with it).

This commit is contained in:
Florent Kermarrec 2024-08-20 12:03:40 +02:00
parent 3a53a92bb2
commit 8f5c2dfbca
1 changed files with 7 additions and 6 deletions
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13
litex/soc/cores/hyperbus.py
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@ -89,8 +89,8 @@ class HyperRAM(LiteXModule):
# Tristates.
# ----------
dq = self.add_tristate(pads.dq) if not hasattr(pads.dq, "oe") else pads.dq
rwds = self.add_tristate(pads.rwds) if not hasattr(pads.rwds, "oe") else pads.rwds
dq = self.add_tristate(pads.dq, register=False) if not hasattr(pads.dq, "oe") else pads.dq
rwds = self.add_tristate(pads.rwds, register=False) if not hasattr(pads.rwds, "oe") else pads.rwds
self.comb += [
# DQ.
dq.o.eq( dq_o),
@ -357,10 +357,11 @@ class HyperRAM(LiteXModule):
t = TristatePads(len(pad))
if register:
for n in range(len(pad)):
self.specials += SDRTristate(pad,
o = t.o[n],
oe = t.oe,
i = t.i[n],
self.specials += SDRTristate(pad[n],
o = t.o[n],
oe = t.oe,
i = t.i[n],
clk = ClockSignal("sys"),
)
else:
self.specials += Tristate(pad,