Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

tools/litex_sim: Disable SDRAM memtest when sdram_init contents provided. 

This avoid corrupting pre-initialized contents or disabling memtest manually.
This commit is contained in:
Florent Kermarrec 2021-02-25 09:06:26 +01:00
parent 80bd4ac4ec
commit 8f5d2ba27f
1 changed files with 7 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
litex/tools/litex_sim.py
View File

@ -216,9 +216,13 @@ class SimSoC(SoCCore):
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = False l2_cache_reverse = False
) )
# Reduce memtest size for simulation speedup if sdram_init != []:
self.add_constant("MEMTEST_DATA_SIZE", 8*1024) # Skip SDRAM test to avoid corrupting pre-initialized contents.
self.add_constant("MEMTEST_ADDR_SIZE", 8*1024) self.add_constant("SDRAM_TEST_DISABLE")
else:
# Reduce memtest size for simulation speedup
self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
#assert not (with_ethernet and with_etherbone) #assert not (with_ethernet and with_etherbone)