regroup all constants/ definitions in common

lib/sata/command/__init__.py

@@ -1,14 +1,7 @@
 from migen.fhdl.std import *
 from migen.genlib.fsm import FSM, NextState
 
-from lib.sata.std import *
-from lib.sata.transport.std import *
-
-regs = {
-	"WRITE_DMA_EXT"			: 0x35,
-	"READ_DMA_EXT"			: 0x25,
-	"IDENTIFY_DEVICE_DMA"	: 0xEE
-}
+from lib.sata.common import *
 
 from_rx = [
 	("dma_activate", 1),

lib/sata/common.py

@@ -2,6 +2,7 @@ from migen.fhdl.std import *
 from migen.genlib.record import *
 from migen.flow.actor import *
 
+# PHY / Link Layers
 primitives = {
 	"ALIGN"	:	0x7B4A4ABC,
 	"CONT"	: 	0X9999AA7C,
@@ -31,9 +32,6 @@ def decode_primitive(dword):
 			return k
 	return ""
 
-def ones(width):
-	return 2**width-1
-
 def phy_layout(dw):
 	layout = [
 		("data", dw),
@@ -48,6 +46,66 @@ def link_layout(dw):
 	]
 	return EndpointDescription(layout, packetized=True)
 
+# Transport Layer
+fis_types = {
+	"REG_H2D":          0x27,
+	"REG_D2H":          0x34,
+	"DMA_ACTIVATE_D2H": 0x39,
+	"DATA":             0x46
+}
+
+class FISField():
+	def __init__(self, dword, offset, width):
+		self.dword = dword
+		self.offset = offset
+		self.width = width
+
+fis_reg_h2d_cmd_len = 5
+fis_reg_h2d_layout = {
+	"type":         FISField(0,  0, 8),
+	"pm_port":      FISField(0,  8, 4),
+	"c":            FISField(0, 15, 1),
+	"command":      FISField(0, 16, 8),
+	"features_lsb": FISField(0, 24, 8),
+
+	"lba_lsb":      FISField(1, 0, 24),
+	"device":       FISField(1, 24, 8),
+
+	"lba_msb":      FISField(2, 0, 24),
+	"features_msb": FISField(2, 24, 8),
+
+	"count":        FISField(3, 0, 16),
+	"icc":          FISField(3, 16, 8),
+	"control":      FISField(3, 24, 8)
+}
+
+fis_reg_d2h_cmd_len = 5
+fis_reg_d2h_layout = {
+	"type":    FISField(0,  0, 8),
+	"pm_port": FISField(0,  8, 4),
+	"i":       FISField(0, 14, 1),
+	"status":  FISField(0, 16, 8),
+	"error":   FISField(0, 24, 8),
+
+	"lba_lsb": FISField(1, 0, 24),
+	"device":  FISField(1, 24, 8),
+
+	"lba_msb": FISField(2, 0, 24),
+
+	"count":   FISField(3, 0, 16)
+}
+
+fis_dma_activate_d2h_cmd_len = 1
+fis_dma_activate_d2h_layout = {
+	"type":    FISField(0,  0, 8),
+	"pm_port": FISField(0,  8, 4)
+}
+
+fis_data_cmd_len = 1
+fis_data_layout = {
+	"type": FISField(0,  0, 8)
+}
+
 def transport_tx_layout(dw):
 	layout = [
 		("type", 8),
@@ -78,6 +136,13 @@ def transport_rx_layout(dw):
 	]
 	return EndpointDescription(layout, packetized=True)
 
+# Command Layer constants / functions
+regs = {
+	"WRITE_DMA_EXT"			: 0x35,
+	"READ_DMA_EXT"			: 0x25,
+	"IDENTIFY_DEVICE_DMA"	: 0xEE
+}
+
 def command_tx_layout(dw):
 	layout = [
 		("write", 1),

lib/sata/link/__init__.py

@@ -2,7 +2,7 @@ from migen.fhdl.std import *
 from migen.genlib.fsm import FSM, NextState
 from migen.actorlib.fifo import SyncFIFO
 
-from lib.sata.std import *
+from lib.sata.common import *
 from lib.sata.link.crc import SATACRCInserter, SATACRCChecker
 from lib.sata.link.scrambler import SATAScrambler
 from lib.sata.link.cont import SATACONTInserter, SATACONTRemover

lib/sata/link/cont.py

@@ -1,7 +1,7 @@
 from migen.fhdl.std import *
 from migen.genlib.misc import optree
 
-from lib.sata.std import *
+from lib.sata.common import *
 from lib.sata.link.scrambler import Scrambler
 
 class SATACONTInserter(Module):

lib/sata/link/crc.py

@@ -2,7 +2,7 @@ from migen.fhdl.std import *
 from migen.genlib.misc import optree
 from migen.actorlib.crc import CRCInserter, CRCChecker
 
-from lib.sata.std import *
+from lib.sata.common import *
 
 class CRCEngine(Module):
 	"""Cyclic Redundancy Check Engine

lib/sata/link/scrambler.py

@@ -1,7 +1,7 @@
 from migen.fhdl.std import *
 from migen.genlib.misc import optree
 
-from lib.sata.std import *
+from lib.sata.common import *
 
 @DecorateModule(InsertCE)
 class Scrambler(Module):

lib/sata/phy/k7sataphy/__init__.py

@@ -1,6 +1,6 @@
 from migen.fhdl.std import *
 
-from lib.sata.std import *
+from lib.sata.common import *
 from lib.sata.phy.k7sataphy.gtx import K7SATAPHYGTX
 from lib.sata.phy.k7sataphy.crg import K7SATAPHYCRG
 from lib.sata.phy.k7sataphy.ctrl import K7SATAPHYHostCtrl, K7SATAPHYDeviceCtrl

lib/sata/phy/k7sataphy/crg.py

@@ -4,7 +4,7 @@ from migen.fhdl.std import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.fsm import FSM, NextState
 
-from lib.sata.std import *
+from lib.sata.common import *
 from lib.sata.phy.k7sataphy.gtx import GTXE2_COMMON
 
 class K7SATAPHYCRG(Module):

lib/sata/phy/k7sataphy/ctrl.py

@@ -5,7 +5,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.fsm import FSM, NextState
 from migen.flow.actor import Sink, Source
 
-from lib.sata.std import *
+from lib.sata.common import *
 
 def us(t, clk_freq):
 	clk_period_us = 1000000/clk_freq

lib/sata/phy/k7sataphy/datapath.py

@@ -3,7 +3,7 @@ from migen.genlib.misc import chooser
 from migen.actorlib.fifo import AsyncFIFO
 from migen.flow.actor import Sink, Source
 
-from lib.sata.std import *
+from lib.sata.common import *
 
 class K7SATAPHYDatapathRX(Module):
 	def __init__(self):

lib/sata/phy/k7sataphy/gtx.py

@@ -1,7 +1,10 @@
 from migen.fhdl.std import *
 from migen.genlib.cdc import *
 
-from lib.sata.std import *
+from lib.sata.common import *
+
+def ones(width):
+	return 2**width-1
 
 class _PulseSynchronizer(PulseSynchronizer):
 	def __init__(self, i, idomain, o, odomain):

lib/sata/test/bfm.py

@@ -2,9 +2,7 @@ import subprocess
 
 from migen.fhdl.std import *
 
-from lib.sata.std import *
-from lib.sata.transport.std import *
-
+from lib.sata.common import *
 from lib.sata.test.common import *
 
 class PHYDword:
@@ -373,12 +371,6 @@ class TransportLayer(Module):
 		else:
 			self.command_callback(fis)
 
-regs = {
-	"WRITE_DMA_EXT"			: 0x35,
-	"READ_DMA_EXT"			: 0x25,
-	"IDENTIFY_DEVICE_DMA"	: 0xEE
-}
-
 class CommandLayer(Module):
 	def __init__(self, transport, debug=False):
 		self.transport = transport

lib/sata/test/command_tb.py

@@ -4,7 +4,7 @@ from migen.fhdl.std import *
 from migen.genlib.record import *
 from migen.sim.generic import run_simulation
 
-from lib.sata.std import *
+from lib.sata.common import *
 from lib.sata.link import SATALink
 from lib.sata.transport import SATATransport
 from lib.sata.command import SATACommand

lib/sata/test/common.py

@@ -1,6 +1,6 @@
 import random
 
-from lib.sata.std import *
+from lib.sata.common import *
 
 def seed_to_data(seed, random=True):
 	if random:

lib/sata/test/crc_tb.py

@@ -2,7 +2,7 @@ import subprocess
 
 from migen.fhdl.std import *
 
-from lib.sata.std import *
+from lib.sata.common import *
 from lib.sata.link.crc import *
 
 from lib.sata.test.common import *

lib/sata/test/link_tb.py

@@ -4,7 +4,7 @@ from migen.fhdl.std import *
 from migen.genlib.record import *
 from migen.sim.generic import run_simulation
 
-from lib.sata.std import *
+from lib.sata.common import *
 from lib.sata.link import SATALink
 
 from lib.sata.test.bfm import *

lib/sata/test/scrambler_tb.py

@@ -2,7 +2,7 @@ import subprocess
 
 from migen.fhdl.std import *
 
-from lib.sata.std import *
+from lib.sata.common import *
 from lib.sata.link.scrambler import *
 
 from lib.sata.test.common import *

lib/sata/test/transport_tb.py

@@ -4,7 +4,7 @@ from migen.fhdl.std import *
 from migen.genlib.record import *
 from migen.sim.generic import run_simulation
 
-from lib.sata.std import *
+from lib.sata.common import *
 from lib.sata.link import SATALink
 from lib.sata.transport import SATATransport
 

lib/sata/transport/__init__.py

@@ -1,8 +1,7 @@
 from migen.fhdl.std import *
 from migen.genlib.fsm import FSM, NextState
 
-from lib.sata.std import *
-from lib.sata.transport.std import *
+from lib.sata.common import *
 
 def _encode_cmd(obj, layout, signal):
 	r = []

lib/sata/transport/std.py

@@ -1,58 +0,0 @@
-fis_types = {
-	"REG_H2D":          0x27,
-	"REG_D2H":          0x34,
-	"DMA_ACTIVATE_D2H": 0x39,
-	"DATA":             0x46
-}
-
-class FISField():
-	def __init__(self, dword, offset, width):
-		self.dword = dword
-		self.offset = offset
-		self.width = width
-
-fis_reg_h2d_cmd_len = 5
-fis_reg_h2d_layout = {
-	"type":         FISField(0,  0, 8),
-	"pm_port":      FISField(0,  8, 4),
-	"c":            FISField(0, 15, 1),
-	"command":      FISField(0, 16, 8),
-	"features_lsb": FISField(0, 24, 8),
-
-	"lba_lsb":      FISField(1, 0, 24),
-	"device":       FISField(1, 24, 8),
-
-	"lba_msb":      FISField(2, 0, 24),
-	"features_msb": FISField(2, 24, 8),
-
-	"count":        FISField(3, 0, 16),
-	"icc":          FISField(3, 16, 8),
-	"control":      FISField(3, 24, 8)
-}
-
-fis_reg_d2h_cmd_len = 5
-fis_reg_d2h_layout = {
-	"type":    FISField(0,  0, 8),
-	"pm_port": FISField(0,  8, 4),
-	"i":       FISField(0, 14, 1),
-	"status":  FISField(0, 16, 8),
-	"error":   FISField(0, 24, 8),
-
-	"lba_lsb": FISField(1, 0, 24),
-	"device":  FISField(1, 24, 8),
-
-	"lba_msb": FISField(2, 0, 24),
-
-	"count":   FISField(3, 0, 16)
-}
-
-fis_dma_activate_d2h_cmd_len = 1
-fis_dma_activate_d2h_layout = {
-	"type":    FISField(0,  0, 8),
-	"pm_port": FISField(0,  8, 4)
-}
-
-fis_data_cmd_len = 1
-fis_data_layout = {
-	"type": FISField(0,  0, 8)
-}

targets/test.py

@@ -8,7 +8,7 @@ from migen.bank.description import *
 from miscope.uart2wishbone import UART2Wishbone
 
 from misoclib import identifier
-from lib.sata.std import *
+from lib.sata.common import *
 from lib.sata.phy.k7sataphy import K7SATAPHY
 
 from migen.genlib.cdc import *