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soc/add_ethernet: Fix add_ethernet.
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@ -1479,7 +1479,7 @@ class LiteXSoC(SoC):
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"eth_rx": phy_cd + "_rx"})(ethmac)
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"eth_rx": phy_cd + "_rx"})(ethmac)
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setattr(self.submodules, name, ethmac)
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setattr(self.submodules, name, ethmac)
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# Compute Regions size and add it to the SoC.
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# Compute Regions size and add it to the SoC.
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ethmac_region_size = (ethmac.rx_slots.read() + ethmac.tx_slots.read())*ethmac.slot_size.read()
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ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant
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ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=ethmac_region_size, cached=False)
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ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=ethmac_region_size, cached=False)
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self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region)
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self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region)
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# Add IRQs (if enabled).
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# Add IRQs (if enabled).
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