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fhdl/verilog: fix signed constant conversion

This commit is contained in:
Sebastien Bourdeauducq 2012-03-06 16:45:44 +01:00
parent 0a23cadd38
commit 90184b22d2
1 changed files with 1 additions and 1 deletions
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2
migen/fhdl/verilog.py
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@ -21,7 +21,7 @@ def _printexpr(ns, node):
if node.n >= 0: if node.n >= 0:
return str(node.bv) + str(node.n) return str(node.bv) + str(node.n)
else: else:
return "-" + str(node.bv) + str(-self.n) return "-" + str(node.bv) + str(-node.n)
elif isinstance(node, Signal): elif isinstance(node, Signal):
return ns.get_name(node) return ns.get_name(node)
elif isinstance(node, _Operator): elif isinstance(node, _Operator):