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cpu/rocket: include core count as per-variant parameter 

Repurpose (and rename to `CPU_SIZE_PARAMS`) the current
`AXI_DATA_WIDTHS` array. In addition to axi widths for
mem and mmio ports, also include each variant's number
of cores, to facilitate dynamically generated per-core
signals.
This commit is contained in:
Gabriel Somlo 2021-09-22 16:48:37 -04:00
parent e6aaa40d2d
commit 901b19828c
1 changed files with 11 additions and 10 deletions
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21
litex/soc/cores/cpu/rocket/core.py
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@ -60,15 +60,15 @@ GCC_FLAGS = {
"full": "-march=rv64imafdc -mabi=lp64 ", "full": "-march=rv64imafdc -mabi=lp64 ",
} }
# AXI Data-Widths ---------------------------------------------------------------------------------- # CPU Size Params ----------------------------------------------------------------------------------
AXI_DATA_WIDTHS = { CPU_SIZE_PARAMS = {
# Variant : (mem, mmio) # Variant : (mem_dw, mmio_dw, num_cores)
"standard": ( 64, 64), "standard": ( 64, 64, 1),
"linux": ( 64, 64), "linux": ( 64, 64, 1),
"linuxd": (128, 64), "linuxd": ( 128, 64, 1),
"linuxq": (256, 64), "linuxq": ( 256, 64, 1),
"full": ( 64, 64), "full": ( 64, 64, 1),
} }
# Rocket RV64 -------------------------------------------------------------------------------------- # Rocket RV64 --------------------------------------------------------------------------------------
@ -111,7 +111,7 @@ class RocketRV64(CPU):
self.reset = Signal() self.reset = Signal()
self.interrupt = Signal(4) self.interrupt = Signal(4)
mem_dw, mmio_dw = AXI_DATA_WIDTHS[self.variant] mem_dw, mmio_dw, num_cores = CPU_SIZE_PARAMS[self.variant]
self.mem_axi = mem_axi = axi.AXIInterface(data_width=mem_dw, address_width=32, id_width=4) self.mem_axi = mem_axi = axi.AXIInterface(data_width=mem_dw, address_width=32, id_width=4)
self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=mmio_dw, address_width=32, id_width=4) self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=mmio_dw, address_width=32, id_width=4)
@ -132,7 +132,6 @@ class RocketRV64(CPU):
i_reset = ResetSignal("sys") | self.reset, i_reset = ResetSignal("sys") | self.reset,
# Debug (ignored). # Debug (ignored).
i_resetctrl_hartIsInReset_0 = Open(),
i_debug_clock = 0, i_debug_clock = 0,
i_debug_reset = ResetSignal() | self.reset, i_debug_reset = ResetSignal() | self.reset,
o_debug_clockeddmi_dmi_req_ready = Open(), o_debug_clockeddmi_dmi_req_ready = Open(),
@ -282,6 +281,8 @@ class RocketRV64(CPU):
o_l2_frontend_bus_axi4_0_r_bits_resp = l2fb_axi.r.resp, o_l2_frontend_bus_axi4_0_r_bits_resp = l2fb_axi.r.resp,
o_l2_frontend_bus_axi4_0_r_bits_last = l2fb_axi.r.last, o_l2_frontend_bus_axi4_0_r_bits_last = l2fb_axi.r.last,
) )
# additional per-core debug signals:
self.cpu_params.update({'i_resetctrl_hartIsInReset_%s'%i : Open() for i in range(num_cores)})
# Adapt AXI interfaces to Wishbone. # Adapt AXI interfaces to Wishbone.
mmio_a2w = ResetInserter()(axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0)) mmio_a2w = ResetInserter()(axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0))